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From: BALATON Zoltan <balaton@eik.bme.hu>
To: Nicholas Piggin <npiggin@gmail.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	 Harsh Prateek Bora <harshpb@linux.ibm.com>,
	 Daniel Henrique Barboza <danielhb413@gmail.com>,
	 Anushree Mathur <anushree.mathur@linux.vnet.ibm.com>,
	 Fabiano Rosas <farosas@suse.de>
Subject: Re: [PATCH 1/4] target/ppc: Fix instruction loading endianness in alignment interrupt
Date: Tue, 20 Jun 2023 16:26:33 +0200 (CEST)	[thread overview]
Message-ID: <393305f2-e785-c3f6-523f-6826b3511cc4@eik.bme.hu> (raw)
In-Reply-To: <20230620131044.169110-2-npiggin@gmail.com>

On Tue, 20 Jun 2023, Nicholas Piggin wrote:
> powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
> after cpu_ldl_code(). This corrects DSISR bits in alignment
> interrupts when running in little endian mode.
>
> Reviewed-by: Fabiano Rosas <farosas@suse.de>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/excp_helper.c | 22 +++++++++++++++++++++-
> 1 file changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 12d8a7257b..a2801f6e6b 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -133,6 +133,26 @@ static void dump_hcall(CPUPPCState *env)
>                   env->nip);
> }
>
> +#ifdef CONFIG_TCG
> +/* Return true iff byteswap is needed to load instruction */
> +static inline bool insn_need_byteswap(CPUArchState *env)
> +{
> +    /* SYSTEM builds TARGET_BIG_ENDIAN. Need to swap when MSR[LE] is set */
> +    return !!(env->msr & ((target_ulong)1 << MSR_LE));
> +}

Don't other places typically use FIELD_EX64 to test for msr bits now? If 
this really only tests for the LE bit and used only once do we need a new 
function for that? I don't quite like trivial one line functions unless it 
does something more complex Because if just makes code harder to read as I 
have to look up what these do when I could just see it right away where it 
used without these functions.

> +
> +static uint32_t ppc_ldl_code(CPUArchState *env, hwaddr addr)
> +{
> +    uint32_t insn = cpu_ldl_code(env, addr);
> +
> +    if (insn_need_byteswap(env)) {
> +        insn = bswap32(insn);
> +    }
> +
> +    return insn;
> +}
> +#endif

Along the same lines I'm not sure this wrapper is needed unless this is a 
recurring operation. Otherwise you could just add the if and the comment 
below at the single place where this is needed. If this will be needed at 
more places later then adding a function may make sense but otherwise I'd 
avoid making code tangled with single line functions defined away from 
where they are used as it's simpler to just have the if and swap at the 
single place where it's needed than adding two new functions that I'd had 
to look up and comprehend first to see what's happening. (It also would be 
just 3 lines instead of 20 that way.)

Regards,
BALATON Zoltan

> +
> static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp)
> {
>     const char *es;
> @@ -3104,7 +3124,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
>
>     /* Restore state and reload the insn we executed, for filling in DSISR.  */
>     cpu_restore_state(cs, retaddr);
> -    insn = cpu_ldl_code(env, env->nip);
> +    insn = ppc_ldl_code(env, env->nip);
>
>     switch (env->mmu_model) {
>     case POWERPC_MMU_SOFT_4xx:
>


  reply	other threads:[~2023-06-20 14:27 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-20 13:10 [PATCH 0/4] target/ppc: Fixes for instruction-related Nicholas Piggin
2023-06-20 13:10 ` [PATCH 1/4] target/ppc: Fix instruction loading endianness in alignment interrupt Nicholas Piggin
2023-06-20 14:26   ` BALATON Zoltan [this message]
2023-06-20 16:54     ` Nicholas Piggin
2023-06-21  5:41       ` Nicholas Piggin
2023-06-20 13:10 ` [PATCH 2/4] target/ppc: Change partition-scope translate interface Nicholas Piggin
2023-06-20 13:10 ` [PATCH 3/4] target/ppc: Add SRR1 prefix indication to interrupt handlers Nicholas Piggin
2023-06-20 13:10 ` [PATCH 4/4] target/ppc: Implement HEIR SPR Nicholas Piggin
2023-06-23  9:31 ` [PATCH 0/4] target/ppc: Fixes for instruction-related Cédric Le Goater
2023-06-28  5:56 ` Anushree Mathur

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