From: "Cédric Le Goater" <clg@kaod.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Nicholas Piggin" <npiggin@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PULL 01/30] target/ppc: gdbstub init spr gdb_id for all CPUs
Date: Mon, 26 Jun 2023 07:56:18 +0200 [thread overview]
Message-ID: <20230626055647.1147743-2-clg@kaod.org> (raw)
In-Reply-To: <20230626055647.1147743-1-clg@kaod.org>
From: Nicholas Piggin <npiggin@gmail.com>
Make sure each CPU gets its state set up for gdb, not just the ones
before PowerPCCPUClass has had its gdb state set up.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/gdbstub.c | 30 +++++++++++++++++++-----------
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 63c9abe4f1b7..ca39efdc357a 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -327,6 +327,25 @@ void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
unsigned int num_regs = 0;
int i;
+ for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
+ ppc_spr_t *spr = &env->spr_cb[i];
+
+ if (!spr->name) {
+ continue;
+ }
+
+ /*
+ * GDB identifies registers based on the order they are
+ * presented in the XML. These ids will not match QEMU's
+ * representation (which follows the PowerISA).
+ *
+ * Store the position of the current register description so
+ * we can make the correspondence later.
+ */
+ spr->gdb_id = num_regs;
+ num_regs++;
+ }
+
if (pcc->gdb_spr_xml) {
return;
}
@@ -348,17 +367,6 @@ void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
g_string_append_printf(xml, " bitsize=\"%d\"", TARGET_LONG_BITS);
g_string_append(xml, " group=\"spr\"/>");
-
- /*
- * GDB identifies registers based on the order they are
- * presented in the XML. These ids will not match QEMU's
- * representation (which follows the PowerISA).
- *
- * Store the position of the current register description so
- * we can make the correspondence later.
- */
- spr->gdb_id = num_regs;
- num_regs++;
}
g_string_append(xml, "</feature>");
--
2.41.0
next prev parent reply other threads:[~2023-06-26 5:57 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-26 5:56 [PULL 00/30] ppc queue Cédric Le Goater
2023-06-26 5:56 ` Cédric Le Goater [this message]
2023-06-26 5:56 ` [PULL 02/30] ppc/pnv/pci: Clean up error messages Cédric Le Goater
2023-06-26 5:56 ` [PULL 03/30] MAINTAINERS: Add reviewers for PowerNV baremetal emulation Cédric Le Goater
2023-06-26 5:56 ` [PULL 04/30] MAINTAINERS: Add reviewer for PowerPC TCG CPUs Cédric Le Goater
2023-06-26 5:56 ` [PULL 05/30] MAINTAINERS: Add reviewer for XIVE Cédric Le Goater
2023-06-26 5:56 ` [PULL 06/30] ppc/prep: Report an error when run with KVM Cédric Le Goater
2023-06-26 5:56 ` [PULL 07/30] ppc/bamboo: " Cédric Le Goater
2023-06-26 5:56 ` [PULL 08/30] ppc/pnv: Rephrase " Cédric Le Goater
2023-06-26 5:56 ` [PULL 09/30] target/ppc: Fix timer register accessors when !KVM Cédric Le Goater
2023-06-26 5:56 ` [PULL 10/30] ppc/spapr: H_ENTER_NESTED should restore host XER ca field Cédric Le Goater
2023-06-26 12:26 ` Michael Tokarev
2023-06-26 21:45 ` Cédric Le Goater
2023-06-26 23:15 ` Nicholas Piggin
2023-06-26 5:56 ` [PULL 11/30] ppc/spapr: Add a nested state struct Cédric Le Goater
2023-06-26 5:56 ` [PULL 12/30] ppc/spapr: load and store l2 state with helper functions Cédric Le Goater
2023-06-26 5:56 ` [PULL 13/30] ppc/spapr: Move spapr nested HV to a new file Cédric Le Goater
2023-06-26 5:56 ` [PULL 14/30] target/ppc: Fix instruction loading endianness in alignment interrupt Cédric Le Goater
2023-06-26 5:56 ` [PULL 15/30] target/ppc: Change partition-scope translate interface Cédric Le Goater
2023-06-26 5:56 ` [PULL 16/30] target/ppc: Add SRR1 prefix indication to interrupt handlers Cédric Le Goater
2023-06-26 5:56 ` [PULL 17/30] target/ppc: Implement HEIR SPR Cédric Le Goater
2023-06-26 5:56 ` [PULL 18/30] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts Cédric Le Goater
2023-06-26 5:56 ` [PULL 19/30] target/ppc: Better CTRL SPR implementation Cédric Le Goater
2023-06-26 5:56 ` [PULL 20/30] target/ppc: Fix sc instruction handling of LEV field Cédric Le Goater
2023-06-26 5:56 ` [PULL 21/30] target/ppc: Add initial flags and helpers for SMT support Cédric Le Goater
2023-06-26 5:56 ` [PULL 22/30] target/ppc: Add support for SMT CTRL register Cédric Le Goater
2023-06-26 5:56 ` [PULL 23/30] target/ppc: Add msgsnd/p and DPDES SMT support Cédric Le Goater
2023-06-26 5:56 ` [PULL 24/30] hw/ppc/spapr: Test whether TCG is enabled with tcg_enabled() Cédric Le Goater
2023-06-26 5:56 ` [PULL 25/30] spapr: TCG allow up to 8-thread SMT on POWER8 and newer CPUs Cédric Le Goater
2023-06-26 5:56 ` [PULL 26/30] tests/avocado: boot ppc64 pseries to Linux VFS mount Cédric Le Goater
2023-06-26 5:56 ` [PULL 27/30] tests/avocado: Add ppc64 pseries multiprocessor boot tests Cédric Le Goater
2023-06-26 5:56 ` [PULL 28/30] pnv/xive2: Add a get_config() method on the presenter class Cédric Le Goater
2023-06-26 5:56 ` [PULL 29/30] pnv/xive2: Check TIMA special ops against a dedicated array for P10 Cédric Le Goater
2023-06-26 5:56 ` [PULL 30/30] tests/avocado: ppc test VOF bios Linux boot Cédric Le Goater
2023-06-26 8:37 ` [PULL 00/30] ppc queue Richard Henderson
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