From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com, philmd@linaro.org
Subject: Re: [PATCH v6 01/20] target/riscv: skip features setup for KVM CPUs
Date: Thu, 29 Jun 2023 10:24:01 +0200 [thread overview]
Message-ID: <20230629-7c5ce376cf635706ec88e266@orel> (raw)
In-Reply-To: <20230628213033.170315-2-dbarboza@ventanamicro.com>
On Wed, Jun 28, 2023 at 06:30:14PM -0300, Daniel Henrique Barboza wrote:
> As it is today it's not possible to use '-cpu host' if the RISC-V host
> has RVH enabled. This is the resulting error:
>
> $ sudo ./qemu/build/qemu-system-riscv64 \
> -machine virt,accel=kvm -m 2G -smp 1 \
> -nographic -snapshot -kernel ./guest_imgs/Image \
> -initrd ./guest_imgs/rootfs_kvm_riscv64.img \
> -append "earlycon=sbi root=/dev/ram rw" \
> -cpu host
> qemu-system-riscv64: H extension requires priv spec 1.12.0
>
> This happens because we're checking for priv spec for all CPUs, and
> since we're not setting env->priv_ver for the 'host' CPU, it's being
> default to zero (i.e. PRIV_SPEC_1_10_0).
>
> In reality env->priv_ver does not make sense when running with the KVM
> 'host' CPU. It's used to gate certain CSRs/extensions during translation
> to make them unavailable if the hart declares an older spec version. It
> doesn't have any other use. E.g. OpenSBI version 1.2 retrieves the spec
> checking if the CSR_MCOUNTEREN, CSR_MCOUNTINHIBIT and CSR_MENVCFG CSRs
> are available [1].
>
> 'priv_ver' is just one example. We're doing a lot of feature validation
> and setup during riscv_cpu_realize() that it doesn't apply to KVM CPUs.
> Validating the feature set for those CPUs is a KVM problem that should
> be handled in KVM specific code.
>
> The new riscv_cpu_realize_tcg() helper contains all validation logic that
> are applicable to TCG CPUs only. riscv_cpu_realize() verifies if we're
> running TCG and, if it's the case, proceed with the usual TCG realize()
> logic.
>
> [1] lib/sbi/sbi_hart.c, hart_detect_features()
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.c | 35 +++++++++++++++++++++++++----------
> 1 file changed, 25 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fb8458bf74..bbb201a2b3 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,7 @@
> #include "migration/vmstate.h"
> #include "fpu/softfloat-helpers.h"
> #include "sysemu/kvm.h"
> +#include "sysemu/tcg.h"
> #include "kvm_riscv.h"
> #include "tcg/tcg.h"
>
> @@ -1308,20 +1309,12 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
> }
> }
>
> -static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> +static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp)
> {
> - CPUState *cs = CPU(dev);
> RISCVCPU *cpu = RISCV_CPU(dev);
> CPURISCVState *env = &cpu->env;
> - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> Error *local_err = NULL;
>
> - cpu_exec_realizefn(cs, &local_err);
> - if (local_err != NULL) {
> - error_propagate(errp, local_err);
> - return;
> - }
> -
> riscv_cpu_validate_misa_mxl(cpu, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> @@ -1356,7 +1349,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
>
> #ifndef CONFIG_USER_ONLY
> - cs->tcg_cflags |= CF_PCREL;
> + CPU(dev)->tcg_cflags |= CF_PCREL;
>
> if (cpu->cfg.ext_sstc) {
> riscv_timer_init(cpu);
> @@ -1369,6 +1362,28 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
> }
> #endif
> +}
> +
> +static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> +{
> + CPUState *cs = CPU(dev);
> + RISCVCPU *cpu = RISCV_CPU(dev);
> + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> + Error *local_err = NULL;
> +
> + cpu_exec_realizefn(cs, &local_err);
> + if (local_err != NULL) {
> + error_propagate(errp, local_err);
> + return;
> + }
> +
> + if (tcg_enabled()) {
> + riscv_cpu_realize_tcg(dev, &local_err);
> + if (local_err != NULL) {
> + error_propagate(errp, local_err);
> + return;
> + }
> + }
>
> riscv_cpu_finalize_features(cpu, &local_err);
> if (local_err != NULL) {
> --
> 2.41.0
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-06-29 8:24 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-28 21:30 [PATCH v6 00/20] target/riscv, KVM: fixes and enhancements Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 01/20] target/riscv: skip features setup for KVM CPUs Daniel Henrique Barboza
2023-06-29 8:24 ` Andrew Jones [this message]
2023-06-28 21:30 ` [PATCH v6 02/20] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set Daniel Henrique Barboza
2023-06-30 7:36 ` Michael Tokarev
2023-06-30 7:46 ` Daniel Henrique Barboza
2023-06-30 7:51 ` Michael Tokarev
2023-06-28 21:30 ` [PATCH v6 03/20] target/riscv/cpu.c: restrict 'mvendorid' value Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 04/20] target/riscv/cpu.c: restrict 'mimpid' value Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 05/20] target/riscv/cpu.c: restrict 'marchid' value Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 06/20] target/riscv: use KVM scratch CPUs to init KVM properties Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 07/20] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 08/20] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 09/20] linux-headers: Update to v6.4-rc1 Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 10/20] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 11/20] target/riscv/cpu: add misa_ext_info_arr[] Daniel Henrique Barboza
2023-06-29 7:26 ` Philippe Mathieu-Daudé
2023-06-29 11:36 ` Daniel Henrique Barboza
2023-06-29 11:43 ` Daniel Henrique Barboza
2023-06-29 8:59 ` Andrew Jones
2023-06-29 11:40 ` Daniel Henrique Barboza
2023-06-29 22:04 ` Daniel Henrique Barboza
2023-06-30 7:21 ` Andrew Jones
2023-06-28 21:30 ` [PATCH v6 12/20] target/riscv: add KVM specific MISA properties Daniel Henrique Barboza
2023-06-29 9:12 ` Andrew Jones
2023-06-29 11:50 ` Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 13/20] target/riscv/kvm.c: update KVM MISA bits Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 14/20] target/riscv/kvm.c: add multi-letter extension KVM properties Daniel Henrique Barboza
2023-06-29 9:14 ` Andrew Jones
2023-06-28 21:30 ` [PATCH v6 15/20] target/riscv/cpu.c: add satp_mode properties earlier Daniel Henrique Barboza
2023-06-29 7:30 ` Philippe Mathieu-Daudé
2023-06-29 9:15 ` Andrew Jones
2023-06-28 21:30 ` [PATCH v6 16/20] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 17/20] target/riscv/cpu.c: create KVM mock properties Daniel Henrique Barboza
2023-06-29 9:17 ` Andrew Jones
2023-06-28 21:30 ` [PATCH v6 18/20] target/riscv: update multi-letter extension KVM properties Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 19/20] target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper Daniel Henrique Barboza
2023-06-28 21:30 ` [PATCH v6 20/20] target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230629-7c5ce376cf635706ec88e266@orel \
--to=ajones@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=dbarboza@ventanamicro.com \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@rivosinc.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.