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From: Minda Chen <minda.chen@starfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Conor Dooley <conor@kernel.org>, Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Roger Quadros <rogerq@kernel.org>
Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-phy@lists.infradead.org>,
	<linux-riscv@lists.infradead.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Minda Chen <minda.chen@starfivetech.com>,
	Mason Huo <mason.huo@starfivetech.com>
Subject: [PATCH v8 5/5] riscv: dts: starfive: Add PCIe PHY dts configuration for JH7110
Date: Thu, 29 Jun 2023 15:51:15 +0800	[thread overview]
Message-ID: <20230629075115.11934-6-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20230629075115.11934-1-minda.chen@starfivetech.com>

Add PCIe PHY dts configuration for StarFive JH7110 SoC.
PCIe0 PHY can be use as USB 3.0 PHY.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..7e5c3ae83aa1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -353,6 +353,18 @@
 			status = "disabled";
 		};
 
+		pciephy0: phy@10210000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10210000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
+		pciephy1: phy@10220000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10220000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
 		uart3: serial@12000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x12000000 0x0 0x10000>;
-- 
2.17.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Minda Chen <minda.chen@starfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Conor Dooley <conor@kernel.org>, Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Roger Quadros <rogerq@kernel.org>
Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-phy@lists.infradead.org>,
	<linux-riscv@lists.infradead.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Minda Chen <minda.chen@starfivetech.com>,
	Mason Huo <mason.huo@starfivetech.com>
Subject: [PATCH v8 5/5] riscv: dts: starfive: Add PCIe PHY dts configuration for JH7110
Date: Thu, 29 Jun 2023 15:51:15 +0800	[thread overview]
Message-ID: <20230629075115.11934-6-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20230629075115.11934-1-minda.chen@starfivetech.com>

Add PCIe PHY dts configuration for StarFive JH7110 SoC.
PCIe0 PHY can be use as USB 3.0 PHY.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..7e5c3ae83aa1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -353,6 +353,18 @@
 			status = "disabled";
 		};
 
+		pciephy0: phy@10210000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10210000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
+		pciephy1: phy@10220000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10220000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
 		uart3: serial@12000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x12000000 0x0 0x10000>;
-- 
2.17.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Minda Chen <minda.chen@starfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Conor Dooley <conor@kernel.org>, Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Roger Quadros <rogerq@kernel.org>
Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-phy@lists.infradead.org>,
	<linux-riscv@lists.infradead.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Minda Chen <minda.chen@starfivetech.com>,
	Mason Huo <mason.huo@starfivetech.com>
Subject: [PATCH v8 5/5] riscv: dts: starfive: Add PCIe PHY dts configuration for JH7110
Date: Thu, 29 Jun 2023 15:51:15 +0800	[thread overview]
Message-ID: <20230629075115.11934-6-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20230629075115.11934-1-minda.chen@starfivetech.com>

Add PCIe PHY dts configuration for StarFive JH7110 SoC.
PCIe0 PHY can be use as USB 3.0 PHY.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..7e5c3ae83aa1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -353,6 +353,18 @@
 			status = "disabled";
 		};
 
+		pciephy0: phy@10210000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10210000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
+		pciephy1: phy@10220000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10220000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
 		uart3: serial@12000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x12000000 0x0 0x10000>;
-- 
2.17.1


  parent reply	other threads:[~2023-06-29  7:52 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-29  7:51 [PATCH v8 0/5] Add JH7110 USB PHY driver support Minda Chen
2023-06-29  7:51 ` Minda Chen
2023-06-29  7:51 ` Minda Chen
2023-06-29  7:51 ` [PATCH v8 1/5] dt-bindings: phy: Add StarFive JH7110 USB PHY Minda Chen
2023-06-29  7:51   ` Minda Chen
2023-06-29  7:51   ` Minda Chen
2023-06-29  7:51 ` [PATCH v8 2/5] dt-bindings: phy: Add StarFive JH7110 PCIe PHY Minda Chen
2023-06-29  7:51   ` Minda Chen
2023-06-29  7:51   ` Minda Chen
2023-06-29  7:51 ` [PATCH v8 3/5] phy: starfive: Add JH7110 USB 2.0 PHY driver Minda Chen
2023-06-29  7:51   ` Minda Chen
2023-06-29  7:51   ` Minda Chen
2023-06-29  7:51 ` [PATCH v8 4/5] phy: starfive: Add JH7110 PCIE " Minda Chen
2023-06-29  7:51   ` Minda Chen
2023-06-29  7:51   ` Minda Chen
2023-06-29  7:51 ` Minda Chen [this message]
2023-06-29  7:51   ` [PATCH v8 5/5] riscv: dts: starfive: Add PCIe PHY dts configuration for JH7110 Minda Chen
2023-06-29  7:51   ` Minda Chen
2023-07-11 11:25 ` (subset) [PATCH v8 0/5] Add JH7110 USB PHY driver support Vinod Koul
2023-07-11 11:25   ` Vinod Koul
2023-07-11 11:25   ` Vinod Koul

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