* [PATCH v2 1/4] target/ppc: Add LPAR-per-core vs per-thread mode flag
2023-07-05 12:06 [PATCH v2 0/4] ppc/pnv: SMT support for powernv Nicholas Piggin
@ 2023-07-05 12:06 ` Nicholas Piggin
2023-07-05 12:06 ` [PATCH v2 2/4] target/ppc: SMT support for the HID SPR Nicholas Piggin
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Nicholas Piggin @ 2023-07-05 12:06 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: Nicholas Piggin, Cédric Le Goater, Frédéric Barrat,
David Gibson, Greg Kurz, Harsh Prateek Bora, qemu-ppc, qemu-devel,
Joel Stanley
The Power ISA has the concept of sub-processors:
Hardware is allowed to sub-divide a multi-threaded processor into
"sub-processors" that appear to privileged programs as multi-threaded
processors with fewer threads.
POWER9 and POWER10 have two modes, either every thread is a
sub-processor or all threads appear as one multi-threaded processor. In
the user manuals these are known as "LPAR per thread" / "Thread LPAR",
and "LPAR per core" / "1 LPAR", respectively.
The practical difference is: in thread LPAR mode, non-hypervisor SPRs
are not shared between threads and msgsndp can not be used to message
siblings. In 1 LPAR mode, some SPRs are shared and msgsndp is usable.
Thrad LPAR allows multiple partitions to run concurrently on the same
core, and is a requirement for KVM to run on POWER9/10 (which does not
gang-schedule an LPAR on all threads of a core like POWER8 KVM).
Traditionally, SMT in PAPR environments including PowerVM and the
pseries QEMU machine with KVM acceleration behaves as in 1 LPAR mode.
In OPAL systems, Thread LPAR is used. When adding SMT to the powernv
machine, it is therefore preferable to emulate Thread LPAR.
To account for this difference between pseries and powernv, an LPAR mode
flag is added such that SPRs can be implemented as per-LPAR shared, and
that becomes either per-thread or per-core depending on the flag.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/spapr_cpu_core.c | 2 ++
target/ppc/cpu.h | 3 +++
target/ppc/cpu_init.c | 12 ++++++++++++
target/ppc/excp_helper.c | 4 ++++
target/ppc/misc_helper.c | 8 ++++++++
target/ppc/translate.c | 11 ++++++-----
6 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index a4e3c2fadd..b482d9754a 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -270,6 +270,8 @@ static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
env->spr_cb[SPR_PIR].default_value = cs->cpu_index;
env->spr_cb[SPR_TIR].default_value = thread_index;
+ cpu_ppc_set_1lpar(cpu);
+
/* Set time-base frequency to 512 MHz. vhyp must be set first. */
cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index af12c93ebc..951f73d89d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -674,6 +674,8 @@ enum {
POWERPC_FLAG_SCV = 0x00200000,
/* Has >1 thread per core */
POWERPC_FLAG_SMT = 0x00400000,
+ /* Using "LPAR per core" mode (as opposed to per-thread) */
+ POWERPC_FLAG_SMT_1LPAR= 0x00800000,
};
/*
@@ -1437,6 +1439,7 @@ void store_booke_tsr(CPUPPCState *env, target_ulong val);
void ppc_tlb_invalidate_all(CPUPPCState *env);
void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
+void cpu_ppc_set_1lpar(PowerPCCPU *cpu);
int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp,
target_ulong address, uint32_t pid);
int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, uint32_t pid);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 5f4969664e..905a59aea9 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6629,6 +6629,18 @@ void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
env->msr_mask &= ~MSR_HVB;
}
+void cpu_ppc_set_1lpar(PowerPCCPU *cpu)
+{
+ CPUPPCState *env = &cpu->env;
+
+ /*
+ * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable
+ * between threads.
+ */
+ if (env->flags & POWERPC_FLAG_SMT) {
+ env->flags |= POWERPC_FLAG_SMT_1LPAR;
+ }
+}
#endif /* !defined(CONFIG_USER_ONLY) */
#endif /* defined(TARGET_PPC64) */
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 354392668e..7683ea0fc9 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -3130,6 +3130,10 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP);
+ if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
+ nr_threads = 1; /* msgsndp behaves as 1-thread in LPAR-per-thread mode*/
+ }
+
if (!dbell_type_server(rb) || ttir >= nr_threads) {
return;
}
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 1f1af21f33..26e546cc9c 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -191,6 +191,10 @@ target_ulong helper_load_dpdes(CPUPPCState *env)
helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP);
+ if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
+ nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */
+ }
+
if (nr_threads == 1) {
if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
dpdes = 1;
@@ -222,6 +226,10 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val)
helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP);
+ if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
+ nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */
+ }
+
if (val & ~(nr_threads - 1)) {
qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "
TARGET_FMT_lx"\n", val);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index db0ba49bdc..4556297ab5 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -246,9 +246,9 @@ static inline bool gen_serialize(DisasContext *ctx)
}
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
-static inline bool gen_serialize_core(DisasContext *ctx)
+static inline bool gen_serialize_core_lpar(DisasContext *ctx)
{
- if (ctx->flags & POWERPC_FLAG_SMT) {
+ if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) {
return gen_serialize(ctx);
}
@@ -451,7 +451,8 @@ static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn)
void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
{
- if (!(ctx->flags & POWERPC_FLAG_SMT)) {
+ if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) {
+ /* CTRL behaves as 1-thread in LPAR-per-thread mode */
spr_write_CTRL_ST(ctx, sprn, gprn);
goto out;
}
@@ -815,7 +816,7 @@ void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
/* DPDES */
void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
{
- if (!gen_serialize_core(ctx)) {
+ if (!gen_serialize_core_lpar(ctx)) {
return;
}
@@ -824,7 +825,7 @@ void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
{
- if (!gen_serialize_core(ctx)) {
+ if (!gen_serialize_core_lpar(ctx)) {
return;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 2/4] target/ppc: SMT support for the HID SPR
2023-07-05 12:06 [PATCH v2 0/4] ppc/pnv: SMT support for powernv Nicholas Piggin
2023-07-05 12:06 ` [PATCH v2 1/4] target/ppc: Add LPAR-per-core vs per-thread mode flag Nicholas Piggin
@ 2023-07-05 12:06 ` Nicholas Piggin
2023-07-05 12:06 ` [PATCH v2 3/4] ppc/pnv: SMT support for powernv Nicholas Piggin
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Nicholas Piggin @ 2023-07-05 12:06 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: Nicholas Piggin, Cédric Le Goater, Frédéric Barrat,
David Gibson, Greg Kurz, Harsh Prateek Bora, qemu-ppc, qemu-devel
HID is a per-core shared register, skiboot sets this (e.g., setting
HILE) on one thread and that must affect all threads of the core.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu_init.c | 2 +-
target/ppc/helper.h | 1 +
target/ppc/misc_helper.c | 21 +++++++++++++++++++++
target/ppc/spr_common.h | 1 +
target/ppc/translate.c | 16 ++++++++++++++++
5 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 905a59aea9..720aad9e05 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5638,7 +5638,7 @@ static void register_power_common_book4_sprs(CPUPPCState *env)
spr_register_hv(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_core_write_generic,
0x00000000);
spr_register_hv(env, SPR_TSCR, "TSCR",
SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 828f7844c8..abec6fe341 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -704,6 +704,7 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl)
DEF_HELPER_2(load_dump_spr, void, env, i32)
DEF_HELPER_2(store_dump_spr, void, env, i32)
+DEF_HELPER_3(spr_core_write_generic, void, env, i32, tl)
DEF_HELPER_3(spr_write_CTRL, void, env, i32, tl)
DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 26e546cc9c..692d058665 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -43,6 +43,27 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
env->spr[sprn]);
}
+void helper_spr_core_write_generic(CPUPPCState *env, uint32_t sprn,
+ target_ulong val)
+{
+ CPUState *cs = env_cpu(env);
+ CPUState *ccs;
+ uint32_t nr_threads = cs->nr_threads;
+ uint32_t core_id = env->spr[SPR_PIR] & ~(nr_threads - 1);
+
+ assert(core_id == env->spr[SPR_PIR] - env->spr[SPR_TIR]);
+
+ if (nr_threads == 1) {
+ env->spr[sprn] = val;
+ return;
+ }
+
+ THREAD_SIBLING_FOREACH(cs, ccs) {
+ CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;
+ cenv->spr[sprn] = val;
+ }
+}
+
void helper_spr_write_CTRL(CPUPPCState *env, uint32_t sprn,
target_ulong val)
{
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index fbf52123b5..5995070eaf 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -82,6 +82,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
+void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4556297ab5..e6a0709066 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -438,6 +438,22 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
#endif
}
+void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn)
+{
+ if (!(ctx->flags & POWERPC_FLAG_SMT)) {
+ spr_write_generic(ctx, sprn, gprn);
+ return;
+ }
+
+ if (!gen_serialize(ctx)) {
+ return;
+ }
+
+ gen_helper_spr_core_write_generic(cpu_env, tcg_constant_i32(sprn),
+ cpu_gpr[gprn]);
+ spr_store_dump_spr(sprn);
+}
+
static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn)
{
/* This does not implement >1 thread */
--
2.40.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 3/4] ppc/pnv: SMT support for powernv
2023-07-05 12:06 [PATCH v2 0/4] ppc/pnv: SMT support for powernv Nicholas Piggin
2023-07-05 12:06 ` [PATCH v2 1/4] target/ppc: Add LPAR-per-core vs per-thread mode flag Nicholas Piggin
2023-07-05 12:06 ` [PATCH v2 2/4] target/ppc: SMT support for the HID SPR Nicholas Piggin
@ 2023-07-05 12:06 ` Nicholas Piggin
2023-07-05 12:06 ` [PATCH v2 4/4] tests/avocado: Add powernv machine test script Nicholas Piggin
2023-07-05 17:04 ` [PATCH v2 0/4] ppc/pnv: SMT support for powernv Daniel Henrique Barboza
4 siblings, 0 replies; 7+ messages in thread
From: Nicholas Piggin @ 2023-07-05 12:06 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: Nicholas Piggin, Cédric Le Goater, Frédéric Barrat,
David Gibson, Greg Kurz, Harsh Prateek Bora, qemu-ppc, qemu-devel
Set the TIR default value with the SMT thread index, and place some
standard limits on SMT configurations. Now powernv is able to boot
skiboot and Linux with a SMT topology, including booting a KVM guest.
There are several SPRs and other features (e.g., broadcast msgsnd)
that are not implemented, but not used by OPAL or Linux and can be
added incrementally.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
docs/system/ppc/powernv.rst | 5 -----
hw/ppc/pnv.c | 12 ++++++++++++
hw/ppc/pnv_core.c | 13 +++++--------
3 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
index c8f9762342..09f3965858 100644
--- a/docs/system/ppc/powernv.rst
+++ b/docs/system/ppc/powernv.rst
@@ -195,11 +195,6 @@ Use a MTD drive to add a PNOR to the machine, and get a NVRAM :
-drive file=./witherspoon.pnor,format=raw,if=mtd
-CAVEATS
--------
-
- * No support for multiple HW threads (SMT=1). Same as pseries.
-
Maintainer contact information
------------------------------
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 5f25fe985a..23740f9d07 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -887,6 +887,18 @@ static void pnv_init(MachineState *machine)
pnv->num_chips =
machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
+
+ if (machine->smp.threads > 8) {
+ error_report("Cannot support more than 8 threads/core "
+ "on a powernv machine");
+ exit(1);
+ }
+ if (!is_power_of_2(machine->smp.threads)) {
+ error_report("Cannot support %d threads/core on a powernv"
+ "machine because it must be a power of 2",
+ machine->smp.threads);
+ exit(1);
+ }
/*
* TODO: should we decide on how many chips we can create based
* on #cores and Venice vs. Murano vs. Naples chip type etc...,
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index ffbc29cbf4..17c267fa61 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -218,12 +218,13 @@ static const MemoryRegionOps pnv_core_power10_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
+static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
+ int thread_index)
{
CPUPPCState *env = &cpu->env;
int core_pir;
- int thread_index = 0; /* TODO: TCG supports only one thread */
ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
+ ppc_spr_t *tir = &env->spr_cb[SPR_TIR];
Error *local_err = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
@@ -239,11 +240,7 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort);
- /*
- * The PIR of a thread is the core PIR + the thread index. We will
- * need to find a way to get the thread index when TCG supports
- * more than 1. We could use the object name ?
- */
+ tir->default_value = thread_index;
pir->default_value = core_pir + thread_index;
/* Set time-base frequency to 512 MHz */
@@ -292,7 +289,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
}
for (j = 0; j < cc->nr_threads; j++) {
- pnv_core_cpu_realize(pc, pc->threads[j], &local_err);
+ pnv_core_cpu_realize(pc, pc->threads[j], &local_err, j);
if (local_err) {
goto err;
}
--
2.40.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v2 4/4] tests/avocado: Add powernv machine test script
2023-07-05 12:06 [PATCH v2 0/4] ppc/pnv: SMT support for powernv Nicholas Piggin
` (2 preceding siblings ...)
2023-07-05 12:06 ` [PATCH v2 3/4] ppc/pnv: SMT support for powernv Nicholas Piggin
@ 2023-07-05 12:06 ` Nicholas Piggin
2023-07-05 14:28 ` Cédric Le Goater
2023-07-05 17:04 ` [PATCH v2 0/4] ppc/pnv: SMT support for powernv Daniel Henrique Barboza
4 siblings, 1 reply; 7+ messages in thread
From: Nicholas Piggin @ 2023-07-05 12:06 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: Nicholas Piggin, Cédric Le Goater, Frédéric Barrat,
David Gibson, Greg Kurz, Harsh Prateek Bora, qemu-ppc, qemu-devel
This copies ppc_pseries.py to start a set of powernv tests, including
a Linux boot test for the newly added SMT mode.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
I didn't add the powernv10 support yet as Cedric suggested, and kept the
same vmlinuz because it's common with the pseries tests. We should do
that in later tests though. Might be time to update default to power10
soon if the model is becoming more complete...
Thanks,
Nick
tests/avocado/ppc_powernv.py | 87 ++++++++++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 tests/avocado/ppc_powernv.py
diff --git a/tests/avocado/ppc_powernv.py b/tests/avocado/ppc_powernv.py
new file mode 100644
index 0000000000..d0e5c07bde
--- /dev/null
+++ b/tests/avocado/ppc_powernv.py
@@ -0,0 +1,87 @@
+# Test that Linux kernel boots on ppc powernv machines and check the console
+#
+# Copyright (c) 2018, 2020 Red Hat, Inc.
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+from avocado.utils import archive
+from avocado_qemu import QemuSystemTest
+from avocado_qemu import wait_for_console_pattern
+
+class powernvMachine(QemuSystemTest):
+
+ timeout = 90
+ KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
+ panic_message = 'Kernel panic - not syncing'
+ good_message = 'VFS: Cannot open root device'
+
+ def do_test_linux_boot(self):
+ self.require_accelerator("tcg")
+ kernel_url = ('https://archives.fedoraproject.org/pub/archive'
+ '/fedora-secondary/releases/29/Everything/ppc64le/os'
+ '/ppc/ppc64/vmlinuz')
+ kernel_hash = '3fe04abfc852b66653b8c3c897a59a689270bc77'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+ self.vm.set_console()
+ kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'console=hvc0'
+ self.vm.add_args('-kernel', kernel_path,
+ '-append', kernel_command_line)
+ self.vm.launch()
+
+ def test_linux_boot(self):
+ """
+ :avocado: tags=arch:ppc64
+ :avocado: tags=machine:powernv
+ :avocado: tags=accel:tcg
+ """
+
+ self.do_test_linux_boot()
+ console_pattern = 'VFS: Cannot open root device'
+ wait_for_console_pattern(self, console_pattern, self.panic_message)
+
+ def test_linux_smp_boot(self):
+ """
+ :avocado: tags=arch:ppc64
+ :avocado: tags=machine:powernv
+ :avocado: tags=accel:tcg
+ """
+
+ self.vm.add_args('-smp', '4')
+ self.do_test_linux_boot()
+ console_pattern = 'smp: Brought up 1 node, 4 CPUs'
+ wait_for_console_pattern(self, console_pattern, self.panic_message)
+ wait_for_console_pattern(self, self.good_message, self.panic_message)
+
+ def test_linux_smt_boot(self):
+ """
+ :avocado: tags=arch:ppc64
+ :avocado: tags=machine:powernv
+ :avocado: tags=accel:tcg
+ """
+
+ self.vm.add_args('-smp', '4,threads=4')
+ self.do_test_linux_boot()
+ console_pattern = 'CPU maps initialized for 4 threads per core'
+ wait_for_console_pattern(self, console_pattern, self.panic_message)
+ console_pattern = 'smp: Brought up 1 node, 4 CPUs'
+ wait_for_console_pattern(self, console_pattern, self.panic_message)
+ wait_for_console_pattern(self, self.good_message, self.panic_message)
+
+ def test_linux_big_boot(self):
+ """
+ :avocado: tags=arch:ppc64
+ :avocado: tags=machine:powernv
+ :avocado: tags=accel:tcg
+ """
+
+ self.vm.add_args('-smp', '16,threads=4,cores=2,sockets=2')
+
+ # powernv does not support NUMA
+ self.do_test_linux_boot()
+ console_pattern = 'CPU maps initialized for 4 threads per core'
+ wait_for_console_pattern(self, console_pattern, self.panic_message)
+ console_pattern = 'smp: Brought up 2 nodes, 16 CPUs'
+ wait_for_console_pattern(self, console_pattern, self.panic_message)
+ wait_for_console_pattern(self, self.good_message, self.panic_message)
--
2.40.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 4/4] tests/avocado: Add powernv machine test script
2023-07-05 12:06 ` [PATCH v2 4/4] tests/avocado: Add powernv machine test script Nicholas Piggin
@ 2023-07-05 14:28 ` Cédric Le Goater
0 siblings, 0 replies; 7+ messages in thread
From: Cédric Le Goater @ 2023-07-05 14:28 UTC (permalink / raw)
To: Nicholas Piggin, Daniel Henrique Barboza
Cc: Frédéric Barrat, David Gibson, Greg Kurz,
Harsh Prateek Bora, qemu-ppc, qemu-devel
On 7/5/23 14:06, Nicholas Piggin wrote:
> This copies ppc_pseries.py to start a set of powernv tests, including
> a Linux boot test for the newly added SMT mode.
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> I didn't add the powernv10 support yet as Cedric suggested, and kept the
> same vmlinuz because it's common with the pseries tests. We should do
> that in later tests though. Might be time to update default to power10
> soon if the model is becoming more complete...
power10 is as good as power9, I would say. power9 has been the default for
4 years now. power9 systems are publicly available though. As you wish.
If we had some ways to deactivate the doorbells when booting Linux, we
would test XIVE with the CPU IPIs also with the tests you introduced.
Pity this wasn't merged :
https://lore.kernel.org/all/20211105102636.1016378-12-clg@kaod.org/
May be it is possible to tweak the CPU features in OPAL with a QEMU
DT property to remove doorbells ?
C.
>
> Thanks,
> Nick
>
> tests/avocado/ppc_powernv.py | 87 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 87 insertions(+)
> create mode 100644 tests/avocado/ppc_powernv.py
>
> diff --git a/tests/avocado/ppc_powernv.py b/tests/avocado/ppc_powernv.py
> new file mode 100644
> index 0000000000..d0e5c07bde
> --- /dev/null
> +++ b/tests/avocado/ppc_powernv.py
> @@ -0,0 +1,87 @@
> +# Test that Linux kernel boots on ppc powernv machines and check the console
> +#
> +# Copyright (c) 2018, 2020 Red Hat, Inc.
> +#
> +# This work is licensed under the terms of the GNU GPL, version 2 or
> +# later. See the COPYING file in the top-level directory.
> +
> +from avocado.utils import archive
> +from avocado_qemu import QemuSystemTest
> +from avocado_qemu import wait_for_console_pattern
> +
> +class powernvMachine(QemuSystemTest):
> +
> + timeout = 90
> + KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
> + panic_message = 'Kernel panic - not syncing'
> + good_message = 'VFS: Cannot open root device'
> +
> + def do_test_linux_boot(self):
> + self.require_accelerator("tcg")
> + kernel_url = ('https://archives.fedoraproject.org/pub/archive'
> + '/fedora-secondary/releases/29/Everything/ppc64le/os'
> + '/ppc/ppc64/vmlinuz')
> + kernel_hash = '3fe04abfc852b66653b8c3c897a59a689270bc77'
> + kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
> +
> + self.vm.set_console()
> + kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'console=hvc0'
> + self.vm.add_args('-kernel', kernel_path,
> + '-append', kernel_command_line)
> + self.vm.launch()
> +
> + def test_linux_boot(self):
> + """
> + :avocado: tags=arch:ppc64
> + :avocado: tags=machine:powernv
> + :avocado: tags=accel:tcg
> + """
> +
> + self.do_test_linux_boot()
> + console_pattern = 'VFS: Cannot open root device'
> + wait_for_console_pattern(self, console_pattern, self.panic_message)
> +
> + def test_linux_smp_boot(self):
> + """
> + :avocado: tags=arch:ppc64
> + :avocado: tags=machine:powernv
> + :avocado: tags=accel:tcg
> + """
> +
> + self.vm.add_args('-smp', '4')
> + self.do_test_linux_boot()
> + console_pattern = 'smp: Brought up 1 node, 4 CPUs'
> + wait_for_console_pattern(self, console_pattern, self.panic_message)
> + wait_for_console_pattern(self, self.good_message, self.panic_message)
> +
> + def test_linux_smt_boot(self):
> + """
> + :avocado: tags=arch:ppc64
> + :avocado: tags=machine:powernv
> + :avocado: tags=accel:tcg
> + """
> +
> + self.vm.add_args('-smp', '4,threads=4')
> + self.do_test_linux_boot()
> + console_pattern = 'CPU maps initialized for 4 threads per core'
> + wait_for_console_pattern(self, console_pattern, self.panic_message)
> + console_pattern = 'smp: Brought up 1 node, 4 CPUs'
> + wait_for_console_pattern(self, console_pattern, self.panic_message)
> + wait_for_console_pattern(self, self.good_message, self.panic_message)
> +
> + def test_linux_big_boot(self):
> + """
> + :avocado: tags=arch:ppc64
> + :avocado: tags=machine:powernv
> + :avocado: tags=accel:tcg
> + """
> +
> + self.vm.add_args('-smp', '16,threads=4,cores=2,sockets=2')
> +
> + # powernv does not support NUMA
> + self.do_test_linux_boot()
> + console_pattern = 'CPU maps initialized for 4 threads per core'
> + wait_for_console_pattern(self, console_pattern, self.panic_message)
> + console_pattern = 'smp: Brought up 2 nodes, 16 CPUs'
> + wait_for_console_pattern(self, console_pattern, self.panic_message)
> + wait_for_console_pattern(self, self.good_message, self.panic_message)
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 0/4] ppc/pnv: SMT support for powernv
2023-07-05 12:06 [PATCH v2 0/4] ppc/pnv: SMT support for powernv Nicholas Piggin
` (3 preceding siblings ...)
2023-07-05 12:06 ` [PATCH v2 4/4] tests/avocado: Add powernv machine test script Nicholas Piggin
@ 2023-07-05 17:04 ` Daniel Henrique Barboza
4 siblings, 0 replies; 7+ messages in thread
From: Daniel Henrique Barboza @ 2023-07-05 17:04 UTC (permalink / raw)
To: Nicholas Piggin
Cc: Cédric Le Goater, Frédéric Barrat, David Gibson,
Greg Kurz, Harsh Prateek Bora, qemu-ppc, qemu-devel
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/5/23 09:06, Nicholas Piggin wrote:
> These patches implement enough to install a distro, boot, run SMP KVM
> guests with libvirt with good performance using MTTCG (as reported by
> Cedric).
>
> There are a few more SPRs that need to be done, and per-LPAR SPRs are
> mostly not annotated yet so it can't run in 1 LPAR mode. But those can
> be added in time, it will take a bit of time to get everything exactly
> as hardware does so I consider this good enough to run common
> software usefully.
>
> Since RFC:
> - Rebased against ppc-next (no conflicts vs upstream anyway).
> - Add patch 4 avocado boot test with SMT, as was added with pseries SMT.
> - Renamed POWERPC_FLAG_1LPAR to POWERPC_FLAG_SMT_1LPAR since it implies
> SMT.
> - Fixed typos, patch 1, 3 changelogs improvement (hopefully).
>
> Since v1:
> - Fix clang compile bug
> - Fix LPAR-per-thread bug in CTRL/DPDES/msgsndp in patch 1
> - Add 2-socket test case to powernv Linux boot avocado test
> - Remove SMT caveat from docs/system/ppc/powernv.rst
>
> Thanks,
> Nick
>
> Nicholas Piggin (4):
> target/ppc: Add LPAR-per-core vs per-thread mode flag
> target/ppc: SMT support for the HID SPR
> ppc/pnv: SMT support for powernv
> tests/avocado: Add powernv machine test script
>
> docs/system/ppc/powernv.rst | 5 ---
> hw/ppc/pnv.c | 12 +++++
> hw/ppc/pnv_core.c | 13 +++---
> hw/ppc/spapr_cpu_core.c | 2 +
> target/ppc/cpu.h | 3 ++
> target/ppc/cpu_init.c | 14 +++++-
> target/ppc/excp_helper.c | 4 ++
> target/ppc/helper.h | 1 +
> target/ppc/misc_helper.c | 29 ++++++++++++
> target/ppc/spr_common.h | 1 +
> target/ppc/translate.c | 27 ++++++++---
> tests/avocado/ppc_powernv.py | 87 ++++++++++++++++++++++++++++++++++++
> 12 files changed, 179 insertions(+), 19 deletions(-)
> create mode 100644 tests/avocado/ppc_powernv.py
>
^ permalink raw reply [flat|nested] 7+ messages in thread