All of lore.kernel.org
 help / color / mirror / Atom feed
From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Anup Patel <apatel@ventanamicro.com>,
	devicetree@vger.kernel.org,
	Saravana Kannan <saravanak@google.com>,
	Anup Patel <anup@brainfault.org>,
	linux-kernel@vger.kernel.org, Conor Dooley <conor@kernel.org>,
	Atish Patra <atishp@atishpatra.org>,
	linux-riscv@lists.infradead.org,
	Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v5 1/9] RISC-V: Add riscv_fw_parent_hartid() function
Date: Mon, 10 Jul 2023 15:13:13 +0530	[thread overview]
Message-ID: <20230710094321.1378351-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com>

We add common riscv_fw_parent_hartid() which help device drivers
to get parent hartid of the INTC (i.e. local interrupt controller)
fwnode. This should work for both DT and ACPI.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/processor.h |  3 +++
 arch/riscv/kernel/cpu.c            | 16 ++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index c950a8d9edef..39dc23a18f88 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -81,6 +81,9 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
 int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid);
 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
 
+struct fwnode_handle;
+int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid);
+
 extern void riscv_fill_hwcap(void);
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
 
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index a2fc952318e9..9be9b3b1f333 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -96,6 +96,22 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
 	return -1;
 }
 
+/* Find hart ID of the CPU fwnode under which given fwnode falls. */
+int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid)
+{
+	int rc;
+	u64 temp;
+
+	if (!is_of_node(node)) {
+		rc = fwnode_property_read_u64_array(node, "hartid", &temp, 1);
+		if (!rc)
+			*hartid = temp;
+	} else
+		rc = riscv_of_parent_hartid(to_of_node(node), hartid);
+
+	return rc;
+}
+
 DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
 
 unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
-- 
2.34.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Atish Patra <atishp@atishpatra.org>,
	Andrew Jones <ajones@ventanamicro.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	Conor Dooley <conor@kernel.org>,
	Saravana Kannan <saravanak@google.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v5 1/9] RISC-V: Add riscv_fw_parent_hartid() function
Date: Mon, 10 Jul 2023 15:13:13 +0530	[thread overview]
Message-ID: <20230710094321.1378351-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230710094321.1378351-1-apatel@ventanamicro.com>

We add common riscv_fw_parent_hartid() which help device drivers
to get parent hartid of the INTC (i.e. local interrupt controller)
fwnode. This should work for both DT and ACPI.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/processor.h |  3 +++
 arch/riscv/kernel/cpu.c            | 16 ++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index c950a8d9edef..39dc23a18f88 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -81,6 +81,9 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid);
 int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid);
 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid);
 
+struct fwnode_handle;
+int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid);
+
 extern void riscv_fill_hwcap(void);
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
 
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index a2fc952318e9..9be9b3b1f333 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -96,6 +96,22 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
 	return -1;
 }
 
+/* Find hart ID of the CPU fwnode under which given fwnode falls. */
+int riscv_fw_parent_hartid(struct fwnode_handle *node, unsigned long *hartid)
+{
+	int rc;
+	u64 temp;
+
+	if (!is_of_node(node)) {
+		rc = fwnode_property_read_u64_array(node, "hartid", &temp, 1);
+		if (!rc)
+			*hartid = temp;
+	} else
+		rc = riscv_of_parent_hartid(to_of_node(node), hartid);
+
+	return rc;
+}
+
 DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
 
 unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
-- 
2.34.1


  reply	other threads:[~2023-07-10  9:43 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-10  9:43 [PATCH v5 0/9] Linux RISC-V AIA Support Anup Patel
2023-07-10  9:43 ` Anup Patel
2023-07-10  9:43 ` Anup Patel [this message]
2023-07-10  9:43   ` [PATCH v5 1/9] RISC-V: Add riscv_fw_parent_hartid() function Anup Patel
2023-07-11 13:26   ` Andrew Jones
2023-07-11 13:26     ` Andrew Jones
2023-07-17  5:04     ` Anup Patel
2023-07-17  5:04       ` Anup Patel
2023-07-10  9:43 ` [PATCH v5 2/9] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-07-10  9:43   ` Anup Patel
2023-07-11 14:12   ` Andrew Jones
2023-07-11 14:12     ` Andrew Jones
2023-07-17  6:38     ` Anup Patel
2023-07-17  6:38       ` Anup Patel
2023-07-10  9:43 ` [PATCH v5 3/9] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-07-10  9:43   ` Anup Patel
2023-07-10  9:43 ` [PATCH v5 4/9] irqchip: Add RISC-V incoming MSI controller driver Anup Patel
2023-07-10  9:43   ` Anup Patel
2023-07-10  9:43 ` [PATCH v5 5/9] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Anup Patel
2023-07-10  9:43   ` Anup Patel
2023-07-10  9:43 ` [PATCH v5 6/9] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-07-10  9:43   ` Anup Patel
2023-07-10  9:43 ` [PATCH v5 7/9] irqchip: Add RISC-V advanced PLIC driver Anup Patel
2023-07-10  9:43   ` Anup Patel
2023-07-13 23:56   ` Saravana Kannan
2023-07-13 23:56     ` Saravana Kannan
2023-07-14  9:01     ` Marc Zyngier
2023-07-14  9:01       ` Marc Zyngier
2023-07-14  9:35       ` Anup Patel
2023-07-14  9:35         ` Anup Patel
2023-07-14 13:35         ` Marc Zyngier
2023-07-14 13:35           ` Marc Zyngier
2023-07-14 14:05           ` Anup Patel
2023-07-14 14:05             ` Anup Patel
2023-07-17  8:05             ` Marc Zyngier
2023-07-17  8:05               ` Marc Zyngier
2023-07-17  9:05               ` Anup Patel
2023-07-17  9:05                 ` Anup Patel
2023-07-17  9:36                 ` Anup Patel
2023-07-17  9:36                   ` Anup Patel
2023-07-17  9:48                 ` Marc Zyngier
2023-07-17  9:48                   ` Marc Zyngier
2023-07-10  9:43 ` [PATCH v5 8/9] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-07-10  9:43   ` Anup Patel
2023-07-10  9:43 ` [PATCH v5 9/9] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2023-07-10  9:43   ` Anup Patel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230710094321.1378351-2-apatel@ventanamicro.com \
    --to=apatel@ventanamicro.com \
    --cc=ajones@ventanamicro.com \
    --cc=anup@brainfault.org \
    --cc=atishp@atishpatra.org \
    --cc=conor@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=maz@kernel.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    --cc=saravanak@google.com \
    --cc=tglx@linutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.