* [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
@ 2023-07-11 22:46 ` Palmer Dabbelt
0 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2023-07-11 22:46 UTC (permalink / raw)
To: Sunil V L; +Cc: linux-riscv, linux-acpi, Palmer Dabbelt
ACPI ISA strings are based on a specification after Zicsr and Zifencei
were split out of I, so we shouldn't be treating them as part of I. We
haven't release an ACPI-based kernel yet, so we don't need to worry
about compatibility with the old ISA strings.
Fixes: 396c018332a1 ("RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
arch/riscv/kernel/cpufeature.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index bdcf460ea53d..a8f66c015229 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
#undef SET_ISA_EXT_MAP
}
- /*
- * Linux requires the following extensions, so we may as well
- * always set them.
- */
- set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
- set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
-
/*
* These ones were as they were part of the base ISA when the
* port & dt-bindings were upstreamed, and so can be set
* unconditionally where `i` is in riscv,isa on DT systems.
*/
if (acpi_disabled) {
+ set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
+ set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
}
--
2.40.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
2023-07-11 22:46 ` Palmer Dabbelt
@ 2023-07-11 22:52 ` Conor Dooley
-1 siblings, 0 replies; 12+ messages in thread
From: Conor Dooley @ 2023-07-11 22:52 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: Sunil V L, linux-riscv, linux-acpi
[-- Attachment #1: Type: text/plain, Size: 2209 bytes --]
On Tue, Jul 11, 2023 at 03:46:00PM -0700, Palmer Dabbelt wrote:
> ACPI ISA strings are based on a specification after Zicsr and Zifencei
> were split out of I, so we shouldn't be treating them as part of I. We
> haven't release an ACPI-based kernel yet, so we don't need to worry
> about compatibility with the old ISA strings.
>
> Fixes: 396c018332a1 ("RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()")
I think, if anything, this is actually:
Fixes: 07edc32779e3 ("RISC-V: always report presence of extensions formerly part of the base ISA")
Although my rationale was that if we get as far as here, then Zicsr and
Zifencei are going to be enabled anyway so there is no harm in setting
it for both. I probably should have been less of a cute hoor though.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> arch/riscv/kernel/cpufeature.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index bdcf460ea53d..a8f66c015229 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
> #undef SET_ISA_EXT_MAP
> }
>
> - /*
> - * Linux requires the following extensions, so we may as well
> - * always set them.
> - */
> - set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> - set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
> -
> /*
> * These ones were as they were part of the base ISA when the
> * port & dt-bindings were upstreamed, and so can be set
> * unconditionally where `i` is in riscv,isa on DT systems.
> */
> if (acpi_disabled) {
> + set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> + set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
> set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
> set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
> }
> --
> 2.40.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
@ 2023-07-11 22:52 ` Conor Dooley
0 siblings, 0 replies; 12+ messages in thread
From: Conor Dooley @ 2023-07-11 22:52 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: linux-acpi, linux-riscv
[-- Attachment #1.1: Type: text/plain, Size: 2209 bytes --]
On Tue, Jul 11, 2023 at 03:46:00PM -0700, Palmer Dabbelt wrote:
> ACPI ISA strings are based on a specification after Zicsr and Zifencei
> were split out of I, so we shouldn't be treating them as part of I. We
> haven't release an ACPI-based kernel yet, so we don't need to worry
> about compatibility with the old ISA strings.
>
> Fixes: 396c018332a1 ("RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()")
I think, if anything, this is actually:
Fixes: 07edc32779e3 ("RISC-V: always report presence of extensions formerly part of the base ISA")
Although my rationale was that if we get as far as here, then Zicsr and
Zifencei are going to be enabled anyway so there is no harm in setting
it for both. I probably should have been less of a cute hoor though.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> arch/riscv/kernel/cpufeature.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index bdcf460ea53d..a8f66c015229 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
> #undef SET_ISA_EXT_MAP
> }
>
> - /*
> - * Linux requires the following extensions, so we may as well
> - * always set them.
> - */
> - set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> - set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
> -
> /*
> * These ones were as they were part of the base ISA when the
> * port & dt-bindings were upstreamed, and so can be set
> * unconditionally where `i` is in riscv,isa on DT systems.
> */
> if (acpi_disabled) {
> + set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> + set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
> set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
> set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
> }
> --
> 2.40.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
2023-07-11 22:52 ` Conor Dooley
@ 2023-07-12 17:05 ` Palmer Dabbelt
-1 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2023-07-12 17:05 UTC (permalink / raw)
To: Conor Dooley; +Cc: Sunil V L, linux-riscv, linux-acpi
On Tue, 11 Jul 2023 15:52:56 PDT (-0700), Conor Dooley wrote:
> On Tue, Jul 11, 2023 at 03:46:00PM -0700, Palmer Dabbelt wrote:
>> ACPI ISA strings are based on a specification after Zicsr and Zifencei
>> were split out of I, so we shouldn't be treating them as part of I. We
>> haven't release an ACPI-based kernel yet, so we don't need to worry
>> about compatibility with the old ISA strings.
>>
>> Fixes: 396c018332a1 ("RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()")
>
> I think, if anything, this is actually:
> Fixes: 07edc32779e3 ("RISC-V: always report presence of extensions formerly part of the base ISA")
>
> Although my rationale was that if we get as far as here, then Zicsr and
> Zifencei are going to be enabled anyway so there is no harm in setting
> it for both. I probably should have been less of a cute hoor though.
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
I think there's no way to get here without the extensions, not 100% sure
though. I'm mainly trying to avoid going down the same rabbit hole of
ISA string compatibility hacks in ACPI that we have for DT, though --
I'm sure we'll end up with a mess as soon as we release, but might as
well catch as much as we can.
>
> Cheers,
> Conor.
>
>> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
>> ---
>> arch/riscv/kernel/cpufeature.c | 9 ++-------
>> 1 file changed, 2 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> index bdcf460ea53d..a8f66c015229 100644
>> --- a/arch/riscv/kernel/cpufeature.c
>> +++ b/arch/riscv/kernel/cpufeature.c
>> @@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
>> #undef SET_ISA_EXT_MAP
>> }
>>
>> - /*
>> - * Linux requires the following extensions, so we may as well
>> - * always set them.
>> - */
>> - set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
>> - set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
>> -
>> /*
>> * These ones were as they were part of the base ISA when the
>> * port & dt-bindings were upstreamed, and so can be set
>> * unconditionally where `i` is in riscv,isa on DT systems.
>> */
>> if (acpi_disabled) {
>> + set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
>> + set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
>> set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
>> set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
>> }
>> --
>> 2.40.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
@ 2023-07-12 17:05 ` Palmer Dabbelt
0 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2023-07-12 17:05 UTC (permalink / raw)
To: Conor Dooley; +Cc: linux-acpi, linux-riscv
On Tue, 11 Jul 2023 15:52:56 PDT (-0700), Conor Dooley wrote:
> On Tue, Jul 11, 2023 at 03:46:00PM -0700, Palmer Dabbelt wrote:
>> ACPI ISA strings are based on a specification after Zicsr and Zifencei
>> were split out of I, so we shouldn't be treating them as part of I. We
>> haven't release an ACPI-based kernel yet, so we don't need to worry
>> about compatibility with the old ISA strings.
>>
>> Fixes: 396c018332a1 ("RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()")
>
> I think, if anything, this is actually:
> Fixes: 07edc32779e3 ("RISC-V: always report presence of extensions formerly part of the base ISA")
>
> Although my rationale was that if we get as far as here, then Zicsr and
> Zifencei are going to be enabled anyway so there is no harm in setting
> it for both. I probably should have been less of a cute hoor though.
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
I think there's no way to get here without the extensions, not 100% sure
though. I'm mainly trying to avoid going down the same rabbit hole of
ISA string compatibility hacks in ACPI that we have for DT, though --
I'm sure we'll end up with a mess as soon as we release, but might as
well catch as much as we can.
>
> Cheers,
> Conor.
>
>> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
>> ---
>> arch/riscv/kernel/cpufeature.c | 9 ++-------
>> 1 file changed, 2 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> index bdcf460ea53d..a8f66c015229 100644
>> --- a/arch/riscv/kernel/cpufeature.c
>> +++ b/arch/riscv/kernel/cpufeature.c
>> @@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
>> #undef SET_ISA_EXT_MAP
>> }
>>
>> - /*
>> - * Linux requires the following extensions, so we may as well
>> - * always set them.
>> - */
>> - set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
>> - set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
>> -
>> /*
>> * These ones were as they were part of the base ISA when the
>> * port & dt-bindings were upstreamed, and so can be set
>> * unconditionally where `i` is in riscv,isa on DT systems.
>> */
>> if (acpi_disabled) {
>> + set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
>> + set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
>> set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
>> set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
>> }
>> --
>> 2.40.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
2023-07-12 17:05 ` Palmer Dabbelt
@ 2023-07-12 17:13 ` Conor Dooley
-1 siblings, 0 replies; 12+ messages in thread
From: Conor Dooley @ 2023-07-12 17:13 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: Sunil V L, linux-riscv, linux-acpi
[-- Attachment #1: Type: text/plain, Size: 789 bytes --]
On Wed, Jul 12, 2023 at 10:05:39AM -0700, Palmer Dabbelt wrote:
> On Tue, 11 Jul 2023 15:52:56 PDT (-0700), Conor Dooley wrote:
> > Although my rationale was that if we get as far as here, then Zicsr and
> > Zifencei are going to be enabled anyway so there is no harm in setting
> > it for both. I probably should have been less of a cute hoor though.
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> I think there's no way to get here without the extensions, not 100% sure
> though. I'm mainly trying to avoid going down the same rabbit hole of ISA
> string compatibility hacks in ACPI that we have for DT, though -- I'm sure
> we'll end up with a mess as soon as we release, but might as well catch as
> much as we can.
Seems reasonable to me chief :+1:
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
@ 2023-07-12 17:13 ` Conor Dooley
0 siblings, 0 replies; 12+ messages in thread
From: Conor Dooley @ 2023-07-12 17:13 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: linux-acpi, linux-riscv
[-- Attachment #1.1: Type: text/plain, Size: 789 bytes --]
On Wed, Jul 12, 2023 at 10:05:39AM -0700, Palmer Dabbelt wrote:
> On Tue, 11 Jul 2023 15:52:56 PDT (-0700), Conor Dooley wrote:
> > Although my rationale was that if we get as far as here, then Zicsr and
> > Zifencei are going to be enabled anyway so there is no harm in setting
> > it for both. I probably should have been less of a cute hoor though.
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> I think there's no way to get here without the extensions, not 100% sure
> though. I'm mainly trying to avoid going down the same rabbit hole of ISA
> string compatibility hacks in ACPI that we have for DT, though -- I'm sure
> we'll end up with a mess as soon as we release, but might as well catch as
> much as we can.
Seems reasonable to me chief :+1:
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_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
2023-07-11 22:46 ` Palmer Dabbelt
@ 2023-07-12 6:42 ` Sunil V L
-1 siblings, 0 replies; 12+ messages in thread
From: Sunil V L @ 2023-07-12 6:42 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: linux-riscv, linux-acpi
On Tue, Jul 11, 2023 at 03:46:00PM -0700, Palmer Dabbelt wrote:
> ACPI ISA strings are based on a specification after Zicsr and Zifencei
> were split out of I, so we shouldn't be treating them as part of I. We
> haven't release an ACPI-based kernel yet, so we don't need to worry
> about compatibility with the old ISA strings.
>
> Fixes: 396c018332a1 ("RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
LGTM. I agree with Conor that Fixes tag should point to 07edc32779e3.
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Thanks,
Sunil
> arch/riscv/kernel/cpufeature.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index bdcf460ea53d..a8f66c015229 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
> #undef SET_ISA_EXT_MAP
> }
>
> - /*
> - * Linux requires the following extensions, so we may as well
> - * always set them.
> - */
> - set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> - set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
> -
> /*
> * These ones were as they were part of the base ISA when the
> * port & dt-bindings were upstreamed, and so can be set
> * unconditionally where `i` is in riscv,isa on DT systems.
> */
> if (acpi_disabled) {
> + set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> + set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
> set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
> set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
> }
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
@ 2023-07-12 6:42 ` Sunil V L
0 siblings, 0 replies; 12+ messages in thread
From: Sunil V L @ 2023-07-12 6:42 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: linux-riscv, linux-acpi
On Tue, Jul 11, 2023 at 03:46:00PM -0700, Palmer Dabbelt wrote:
> ACPI ISA strings are based on a specification after Zicsr and Zifencei
> were split out of I, so we shouldn't be treating them as part of I. We
> haven't release an ACPI-based kernel yet, so we don't need to worry
> about compatibility with the old ISA strings.
>
> Fixes: 396c018332a1 ("RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
LGTM. I agree with Conor that Fixes tag should point to 07edc32779e3.
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Thanks,
Sunil
> arch/riscv/kernel/cpufeature.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index bdcf460ea53d..a8f66c015229 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
> #undef SET_ISA_EXT_MAP
> }
>
> - /*
> - * Linux requires the following extensions, so we may as well
> - * always set them.
> - */
> - set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> - set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
> -
> /*
> * These ones were as they were part of the base ISA when the
> * port & dt-bindings were upstreamed, and so can be set
> * unconditionally where `i` is in riscv,isa on DT systems.
> */
> if (acpi_disabled) {
> + set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> + set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
> set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
> set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
> }
> --
> 2.40.1
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] RISC-V: Don't include Zicsr or Zifencei in I from ACPI
2023-07-11 22:46 ` Palmer Dabbelt
@ 2023-07-13 23:50 ` patchwork-bot+linux-riscv
-1 siblings, 0 replies; 12+ messages in thread
From: patchwork-bot+linux-riscv @ 2023-07-13 23:50 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: linux-riscv, sunilvl, linux-acpi
Hello:
This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Tue, 11 Jul 2023 15:46:00 -0700 you wrote:
> ACPI ISA strings are based on a specification after Zicsr and Zifencei
> were split out of I, so we shouldn't be treating them as part of I. We
> haven't release an ACPI-based kernel yet, so we don't need to worry
> about compatibility with the old ISA strings.
>
> Fixes: 396c018332a1 ("RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap()")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> [...]
Here is the summary with links:
- RISC-V: Don't include Zicsr or Zifencei in I from ACPI
https://git.kernel.org/riscv/c/ab2dbc7acced
You are awesome, thank you!
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