[chrome-os:chromeos-6.1 27/28] sound/soc/amd/acp/acp-phoenix.c:277:6: warning: no previous prototype for 'acp63_master_clock_generate'

[chrome-os:chromeos-6.1 27/28] sound/soc/amd/acp/acp-phoenix.c:277:6: warning: no previous prototype for 'acp63_master_clock_generate'

[kernel test robot]

tree:   https://chromium.googlesource.com/chromiumos/third_party/kernel chromeos-6.1
head:   b98aa1b68171dec7de67a310b14063e9919a9295
commit: f81943476e13ef73cf78759efbacd674cbfcf5e0 [27/28] CHROMIUM: ASoC: amd: acp: Legacy Phoenix driver support.
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20230719/202307192248.eS3oPL41-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce: (https://download.01.org/0day-ci/archive/20230719/202307192248.eS3oPL41-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202307192248.eS3oPL41-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> sound/soc/amd/acp/acp-phoenix.c:277:6: warning: no previous prototype for 'acp63_master_clock_generate' [-Wmissing-prototypes]
     277 | void acp63_master_clock_generate(struct acp_dev_data *adata)
         |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~


vim +/acp63_master_clock_generate +277 sound/soc/amd/acp/acp-phoenix.c

   276	
 > 277	void acp63_master_clock_generate(struct acp_dev_data *adata)
   278	{
   279	        u32 data;
   280	        union clk5_pll_req_no clk5_pll;
   281	        struct pci_dev *smn_dev;
   282	
   283	        smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x14E8, NULL);
   284	        if (!smn_dev) {
   285	                pr_err("sujith Failed to get host bridge device\n");
   286	                return;
   287	        }
   288	        /* Clk5 pll register values to get mclk as 196.6MHz*/
   289	        clk5_pll.bits.fb_mult_int = 0x31;
   290	        clk5_pll.bits.pll_spine_div = 0;
   291	        clk5_pll.bits.gb_mult_frac = 0x26E9;
   292	
   293	        data = smn_read(smn_dev, CLK5_CLK_PLL_PWR_REQ_N0);
   294	        smn_write(smn_dev, CLK5_CLK_PLL_PWR_REQ_N0, data | PLL_AUTO_STOP_REQ);
   295	
   296	        data = smn_read(smn_dev, CLK5_SPLL_FIELD_2_N0);
   297	        if (data & PLL_FRANCE_EN)
   298	                smn_write(smn_dev, CLK5_SPLL_FIELD_2_N0, data | PLL_FRANCE_EN);
   299	
   300	        smn_write(smn_dev, CLK5_CLK_PLL_REQ_N0, clk5_pll.clk5_pll_req_no_reg);
   301	
   302	        data = smn_read(smn_dev, CLK5_CLK_PLL_PWR_REQ_N0);
   303	        smn_write(smn_dev, CLK5_CLK_PLL_PWR_REQ_N0, data | PLL_AUTO_START_REQ);
   304	
   305	        data = smn_read(smn_dev, CLK5_CLK_DFSBYPASS_CONTR);
   306	        smn_write(smn_dev, CLK5_CLK_DFSBYPASS_CONTR, data | EXIT_DPF_BYPASS_0);
   307	        smn_write(smn_dev, CLK5_CLK_DFSBYPASS_CONTR, data | EXIT_DPF_BYPASS_1);
   308	
   309	        smn_write(smn_dev, CLK5_CLK_DFS_CNTL_N0, CLK0_DIVIDER);
   310	}
   311	

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