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From: Minda Chen <minda.chen@starfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Subject: [dt-for-next v1 1/2] riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110
Date: Wed, 26 Jul 2023 03:06:08 -0700	[thread overview]
Message-ID: <20230726100609.72550-2-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20230726100609.72550-1-minda.chen@starfivetech.com>

Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 90aabeac7b51..dbc1243a0e75 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -446,6 +446,27 @@ i2c2: i2c@10050000 {
 			status = "disabled";
 		};
 
+		usbphy0: phy@10200000 {
+			compatible = "starfive,jh7110-usb-phy";
+			reg = <0x0 0x10200000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+				 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
+			clock-names = "125m", "app_125m";
+			#phy-cells = <0>;
+		};
+
+		pciephy0: phy@10210000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10210000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
+		pciephy1: phy@10220000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10220000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
 		stgcrg: clock-controller@10230000 {
 			compatible = "starfive,jh7110-stgcrg";
 			reg = <0x0 0x10230000 0x0 0x10000>;
-- 
2.25.1


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WARNING: multiple messages have this Message-ID (diff)
From: Minda Chen <minda.chen@starfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Subject: [dt-for-next v1 1/2] riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110
Date: Wed, 26 Jul 2023 03:06:08 -0700	[thread overview]
Message-ID: <20230726100609.72550-2-minda.chen@starfivetech.com> (raw)
In-Reply-To: <20230726100609.72550-1-minda.chen@starfivetech.com>

Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 90aabeac7b51..dbc1243a0e75 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -446,6 +446,27 @@ i2c2: i2c@10050000 {
 			status = "disabled";
 		};
 
+		usbphy0: phy@10200000 {
+			compatible = "starfive,jh7110-usb-phy";
+			reg = <0x0 0x10200000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+				 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
+			clock-names = "125m", "app_125m";
+			#phy-cells = <0>;
+		};
+
+		pciephy0: phy@10210000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10210000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
+		pciephy1: phy@10220000 {
+			compatible = "starfive,jh7110-pcie-phy";
+			reg = <0x0 0x10220000 0x0 0x10000>;
+			#phy-cells = <0>;
+		};
+
 		stgcrg: clock-controller@10230000 {
 			compatible = "starfive,jh7110-stgcrg";
 			reg = <0x0 0x10230000 0x0 0x10000>;
-- 
2.25.1


  reply	other threads:[~2023-07-26 10:07 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-26 10:06 [dt-for-next v1 0/2] Add USB PHY and USB dts node for JH7110 Minda Chen
2023-07-26 10:06 ` Minda Chen
2023-07-26 10:06 ` Minda Chen [this message]
2023-07-26 10:06   ` [dt-for-next v1 1/2] riscv: dts: starfive: Add USB and PCIe PHY nodes " Minda Chen
2023-07-26 10:06 ` [dt-for-next v1 2/2] riscv: dts: starfive: Add USB dts node " Minda Chen
2023-07-26 10:06   ` Minda Chen
2023-07-26 16:15 ` [dt-for-next v1 0/2] Add USB PHY and " Conor Dooley
2023-07-26 16:15   ` Conor Dooley

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