Re: [PATCH v5 3/5] arm64: dts: ti: k3-am64 : Add M4F remote proc node

From: Nishanth Menon <nm@ti.com>
To: Hari Nagalla <hnagalla@ti.com>
Cc: <andersson@kernel.org>, <mathieu.poirier@linaro.org>,
	<p.zabel@pengutronix.de>, <martyn.welch@collabora.com>,
	<vigneshr@ti.com>, <kristo@kernel.org>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
	<linux-remoteproc@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>
Subject: Re: [PATCH v5 3/5] arm64: dts: ti: k3-am64 : Add M4F remote proc node
Date: Tue, 8 Aug 2023 07:08:06 -0500	[thread overview]
Message-ID: <20230808120806.5ymcvsqgg2kv65qq@arson> (raw)
In-Reply-To: <20230808044529.25925-4-hnagalla@ti.com>

On 23:45-20230807, Hari Nagalla wrote:
> The AM64x SoCs of the TI K3 family have a Cortex M4F core in the MCU
> domain. This core can be used by non safety applications as a remote
> processor. When used as a remote processor with virtio/rpmessage IPC,
> two carveout reserved memory nodes are needed. The first region is used
> as a DMA pool for the rproc device, and the second region will furnish
> the static carveout regions for the firmware memory.
> 
> The current carveout addresses and sizes are defined statically for
> each rproc device. The M4F processor do not have an MMU, and as such
> require the exact memory used by the firmware to be set-aside.
> 
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> ---
> Changes in v5:
>  - Add M4F device node patches to the patch list

This will need to be reviewed after driver changes are complete and
should go through the SoC tree.

> 
>  arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 12 ++++++++++++
>  arch/arm64/boot/dts/ti/k3-am642-evm.dts | 18 ++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am642-sk.dts  | 18 ++++++++++++++++++
>  3 files changed, 48 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
> index 686d49790721..4151d0057bc8 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi
> @@ -158,4 +158,16 @@ mcu_esm: esm@4100000 {
>  		reg = <0x00 0x4100000 0x00 0x1000>;
>  		ti,esm-pins = <0>, <1>;
>  	};
> +
> +	mcu_m4fss: m4fss@5000000 {
> +		compatible = "ti,am64-m4fss";
> +		reg = <0x00 0x5000000 0x00 0x30000>,
> +		<0x00 0x5040000 0x00 0x10000>;
> +		reg-names = "iram", "dram";
> +		ti,sci = <&dmsc>;
> +		ti,sci-dev-id = <9>;
> +		ti,sci-proc-ids = <0x18 0xff>;
> +		resets = <&k3_reset 9 1>;
> +		firmware-name = "am64-mcu-m4f0_0-fw";
> +	};
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index d84e7ee16032..4fd1dc162534 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -99,6 +99,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
>  			no-map;
>  		};
>  
> +		mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x00 0xa4000000 0x00 0x100000>;
> +			no-map;
> +		};
> +
> +		mcu_m4fss_memory_region: m4f-memory@a4100000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x00 0xa4100000 0x00 0xf00000>;
> +			no-map;
> +		};
> +
>  		rtos_ipc_memory_region: ipc-memories@a5000000 {
>  			reg = <0x00 0xa5000000 0x00 0x00800000>;
>  			alignment = <0x1000>;
> @@ -639,6 +651,12 @@ &main_r5fss1_core1 {
>  			<&main_r5fss1_core1_memory_region>;
>  };
>  
> +&mcu_m4fss {
> +	mboxes = <&mailbox0_cluster6>, <&mbox_m4_0>;
> +	memory-region = <&mcu_m4fss_dma_memory_region>,
> +			<&mcu_m4fss_memory_region>;
> +};
> +
>  &serdes_ln_ctrl {
>  	idle-states = <AM64_SERDES0_LANE0_PCIE0>;
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> index 963d796a3a97..f919dd5ba9ba 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> @@ -98,6 +98,18 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
>  			no-map;
>  		};
>  
> +		mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x00 0xa4000000 0x00 0x100000>;
> +			no-map;
> +		};
> +
> +		mcu_m4fss_memory_region: m4f-memory@a4100000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x00 0xa4100000 0x00 0xf00000>;
> +			no-map;
> +		};
> +
>  		rtos_ipc_memory_region: ipc-memories@a5000000 {
>  			reg = <0x00 0xa5000000 0x00 0x00800000>;
>  			alignment = <0x1000>;
> @@ -637,6 +649,12 @@ &main_r5fss1_core1 {
>  			<&main_r5fss1_core1_memory_region>;
>  };
>  
> +&mcu_m4fss {
> +	mboxes = <&mailbox0_cluster6>, <&mbox_m4_0>;
> +	memory-region = <&mcu_m4fss_dma_memory_region>,
> +			<&mcu_m4fss_memory_region>;
> +};
> +
>  &ecap0 {
>  	status = "okay";
>  	/* PWM is available on Pin 1 of header J3 */
> -- 
> 2.34.1
> 

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D