[Buildroot] [PATCH 0/3] Update RISC-V Instruction Sets

[Buildroot] [PATCH 0/3] Update RISC-V Instruction Sets

[Jamie Gibbons via buildroot]

Hi all,

As per an earlier discussion with Thomas Petazzoni, we have decided that
it best to update the RISC-V instruction sets. This patch series updates
the kconfig to allow C and V to be selected as part of the general
purpose instruction set, thus allowing IMAFD + C and IMAFD + V to be a
part of a general purpose selection and keeping other configurations as
custom.
With this I have updated the microchip_mpfs_icicle_defconfig to make use
of these changes.
Finally, I have included a fix to the post-image script to allow an
sdcard.img to be built for the Microchip MPFS Icicle kit. When merging,
some changes were made that broke this. The hss-payload-generator tool
looks for the u-boot.bin image in the directory this command is run
from. This binary file is located in the output images directory. All
changes to this script were made to try to ensure optimise paths and
methods while achieving a working solution.
This patch set is indended to be applied to the next branch as that is
where the Microchip Icicle kit patch series has previously been applied.

Looking forward to your feedback.

Regards,
Jamie.

Jamie Gibbons (3):
  arch/Config.in.riscv: update instruction set ext
  configs/microchip_mpfs_icicle_defconfig: update instruction sets
  board/microchip/mpfs_icicle: update post-image script

 arch/Config.in.riscv                      | 24 ++++++++++++++---------
 board/microchip/mpfs_icicle/post-image.sh |  6 ++++--
 configs/microchip_mpfs_icicle_defconfig   |  5 +----
 3 files changed, 20 insertions(+), 15 deletions(-)

-- 
2.34.1

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[Buildroot] [PATCH 1/3] arch/Config.in.riscv: update instruction set ext

[Jamie Gibbons via buildroot]

Allow a RISC-V G core to support C and V. Move custom RVC and RVV
instructions from RISC-V custom core to RISC-V general core.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
---
 arch/Config.in.riscv | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index 3dfbb4165f..ab839fd8a4 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -35,6 +35,21 @@ config BR2_riscv_g
 	help
 	  General purpose (G) is equivalent to IMAFD.
 
+if BR2_riscv_g
+
+comment "Instruction Set Extensions"
+
+config BR2_RISCV_ISA_CUSTOM_RVC
+	bool "Compressed Instructions (C)"
+	select BR2_RISCV_ISA_RVC
+
+config BR2_RISCV_ISA_CUSTOM_RVV
+	bool "Vector Instructions (V)"
+	select BR2_RISCV_ISA_RVV
+	select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
+
+endif
+
 config BR2_riscv_custom
 	bool "Custom architecture"
 	select BR2_RISCV_ISA_RVI
@@ -62,15 +77,6 @@ config BR2_RISCV_ISA_CUSTOM_RVD
 	depends on BR2_RISCV_ISA_RVF
 	select BR2_RISCV_ISA_RVD
 
-config BR2_RISCV_ISA_CUSTOM_RVC
-	bool "Compressed Instructions (C)"
-	select BR2_RISCV_ISA_RVC
-
-config BR2_RISCV_ISA_CUSTOM_RVV
-	bool "Vector Instructions (V)"
-	select BR2_RISCV_ISA_RVV
-	select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
-
 endif
 
 choice
-- 
2.34.1

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[Buildroot] [PATCH 2/3] configs/microchip_mpfs_icicle_defconfig: update instruction sets

[Jamie Gibbons via buildroot]

Update the instruction sets for MPFS icicle kit to mirror the
configuration update, i.e. It is now classed as a RISC-V G core with
support for C, IMAFDC.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
---
 configs/microchip_mpfs_icicle_defconfig | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig
index b2568cae6a..a3b3093982 100644
--- a/configs/microchip_mpfs_icicle_defconfig
+++ b/configs/microchip_mpfs_icicle_defconfig
@@ -1,8 +1,5 @@
 BR2_riscv=y
-BR2_riscv_custom=y
-BR2_RISCV_ISA_CUSTOM_RVM=y
-BR2_RISCV_ISA_CUSTOM_RVF=y
-BR2_RISCV_ISA_CUSTOM_RVD=y
+BR2_riscv_g=y
 BR2_RISCV_ISA_CUSTOM_RVC=y
 BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_1=y
 BR2_TARGET_GENERIC_HOSTNAME="mpfs_icicle"
-- 
2.34.1

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[Buildroot] [PATCH 3/3] board/microchip/mpfs_icicle: update post-image script

[Jamie Gibbons via buildroot]

The hss-payload-generator could not find where u-boot.bin was when
looking for it using the config.yaml. This needs to be ran in the
same directory as the u-boot.bin file to enable it to find it. Fix the
post image script to allow an image to get built.

Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
---
 board/microchip/mpfs_icicle/post-image.sh | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/microchip/mpfs_icicle/post-image.sh b/board/microchip/mpfs_icicle/post-image.sh
index 04b34bbd40..2368aa42f6 100755
--- a/board/microchip/mpfs_icicle/post-image.sh
+++ b/board/microchip/mpfs_icicle/post-image.sh
@@ -2,7 +2,9 @@
 HSS_PAYLOAD_GENERATOR=${HOST_DIR}/bin/hss-payload-generator
 MKIMAGE=${HOST_DIR}/bin/mkimage
 
-"${HSS_PAYLOAD_GENERATOR}" -c board/microchip/mpfs_icicle/config.yaml "${BINARIES_DIR}"/payload.bin
-cp board/microchip/mpfs_icicle/mpfs_icicle.its "${BINARIES_DIR}"/mpfs_icicle.its
+cd "${BINARIES_DIR}" || exit
+"${HSS_PAYLOAD_GENERATOR}" -c "${CONFIG_DIR}"/board/microchip/mpfs_icicle/config.yaml payload.bin
+cd "${CONFIG_DIR}" || exit
+cp "${CONFIG_DIR}"/board/microchip/mpfs_icicle/mpfs_icicle.its "${BINARIES_DIR}"/mpfs_icicle.its
 (cd "${BINARIES_DIR}" && "${MKIMAGE}" -f mpfs_icicle.its mpfs_icicle.itb)
 support/scripts/genimage.sh -c board/microchip/mpfs_icicle/genimage.cfg
-- 
2.34.1

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Re: [Buildroot] [PATCH 1/3] arch/Config.in.riscv: update instruction set ext

[Thomas Petazzoni via buildroot]

On Tue, 15 Aug 2023 11:05:58 +0100
Jamie Gibbons via buildroot <buildroot@buildroot.org> wrote:

> +if BR2_riscv_g
> +
> +comment "Instruction Set Extensions"
> +
> +config BR2_RISCV_ISA_CUSTOM_RVC
> +	bool "Compressed Instructions (C)"
> +	select BR2_RISCV_ISA_RVC
> +
> +config BR2_RISCV_ISA_CUSTOM_RVV
> +	bool "Vector Instructions (V)"
> +	select BR2_RISCV_ISA_RVV
> +	select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
> +
> +endif

I believe this is still not correct: now those options are only
available for the BR2_riscv_g case, no longer for the custom RISC-V
core case.

Those two options should be available both as add-ons for the riscv_g
*and* for the riscv custom cases.

Best regards,

Thomas
-- 
Thomas Petazzoni, co-owner and CEO, Bootlin
Embedded Linux and Kernel engineering and training
https://bootlin.com
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Re: [Buildroot] [PATCH 1/3] arch/Config.in.riscv: update instruction set ext

[Jamie.Gibbons--- via buildroot]

Hi Thomas,

On Tue, 2023-08-15 at 21:38 +0200, Thomas Petazzoni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On Tue, 15 Aug 2023 11:05:58 +0100
> Jamie Gibbons via buildroot <buildroot@buildroot.org> wrote:
> 
> > +if BR2_riscv_g
> > +
> > +comment "Instruction Set Extensions"
> > +
> > +config BR2_RISCV_ISA_CUSTOM_RVC
> > +     bool "Compressed Instructions (C)"
> > +     select BR2_RISCV_ISA_RVC
> > +
> > +config BR2_RISCV_ISA_CUSTOM_RVV
> > +     bool "Vector Instructions (V)"
> > +     select BR2_RISCV_ISA_RVV
> > +     select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
> > +
> > +endif
> 
> I believe this is still not correct: now those options are only
> available for the BR2_riscv_g case, no longer for the custom RISC-V
> core case.
> 
> Those two options should be available both as add-ons for the riscv_g
> *and* for the riscv custom cases.
> 
Apologies, I misunderstood your suggestion to "move" the options. I
will update this and send a v2.

Regards,

Jamie.


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