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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: igt-dev@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
	intel-xe@lists.freedesktop.org
Subject: [igt-dev] [PATCH igt 4/4] tests/xe_debugfs: skip page table level check for Xe2
Date: Tue, 29 Aug 2023 07:11:07 -0700	[thread overview]
Message-ID: <20230829141107.1505705-5-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20230829141107.1505705-1-lucas.demarchi@intel.com>

From: Janga Rahul Kumar <janga.rahul.kumar@intel.com>

Starting with Xe2, a 5-level page table is always used, regardless of
the actual virtual address range supported by the platform. Do not
depend on VA range to configure max page table level.

Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/xe/xe_debugfs.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/tests/xe/xe_debugfs.c b/tests/xe/xe_debugfs.c
index e51d03661..72c069bfc 100644
--- a/tests/xe/xe_debugfs.c
+++ b/tests/xe/xe_debugfs.c
@@ -74,6 +74,7 @@ static int validate_entries(int fd, const char *add_path, const char * const str
 static void
 test_base(int fd, struct drm_xe_query_config *config)
 {
+	uint16_t devid = intel_get_drm_devid(fd);
 	static const char * const expected_files[] = {
 		"gt0",
 		"gt1",
@@ -86,7 +87,6 @@ test_base(int fd, struct drm_xe_query_config *config)
 		"clients",
 		"name"
 	};
-
 	char reference[4096];
 	int val = 0;
 
@@ -104,16 +104,19 @@ test_base(int fd, struct drm_xe_query_config *config)
 
 	igt_assert(igt_debugfs_search(fd, "info", reference));
 
-	switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
-	case 48:
-		val = 3;
-		break;
-	case 57:
-		val = 4;
-		break;
+	if (!AT_LEAST_GEN(devid, 20)) {
+		switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
+		case 48:
+			val = 3;
+			break;
+		case 57:
+			val = 4;
+			break;
+		}
+
+		sprintf(reference, "vm_max_level %d", val);
+		igt_assert(igt_debugfs_search(fd, "info", reference));
 	}
-	sprintf(reference, "vm_max_level %d", val);
-	igt_assert(igt_debugfs_search(fd, "info", reference));
 
 	igt_assert(igt_debugfs_exists(fd, "gt0", O_RDONLY));
 	if (config->info[XE_QUERY_CONFIG_GT_COUNT] > 1)
-- 
2.40.1

WARNING: multiple messages have this Message-ID (diff)
From: Lucas De Marchi <lucas.demarchi@intel.com>
To: igt-dev@lists.freedesktop.org
Cc: Janga Rahul Kumar <janga.rahul.kumar@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	intel-xe@lists.freedesktop.org
Subject: [Intel-xe] [PATCH igt 4/4] tests/xe_debugfs: skip page table level check for Xe2
Date: Tue, 29 Aug 2023 07:11:07 -0700	[thread overview]
Message-ID: <20230829141107.1505705-5-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20230829141107.1505705-1-lucas.demarchi@intel.com>

From: Janga Rahul Kumar <janga.rahul.kumar@intel.com>

Starting with Xe2, a 5-level page table is always used, regardless of
the actual virtual address range supported by the platform. Do not
depend on VA range to configure max page table level.

Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 tests/xe/xe_debugfs.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

diff --git a/tests/xe/xe_debugfs.c b/tests/xe/xe_debugfs.c
index e51d03661..72c069bfc 100644
--- a/tests/xe/xe_debugfs.c
+++ b/tests/xe/xe_debugfs.c
@@ -74,6 +74,7 @@ static int validate_entries(int fd, const char *add_path, const char * const str
 static void
 test_base(int fd, struct drm_xe_query_config *config)
 {
+	uint16_t devid = intel_get_drm_devid(fd);
 	static const char * const expected_files[] = {
 		"gt0",
 		"gt1",
@@ -86,7 +87,6 @@ test_base(int fd, struct drm_xe_query_config *config)
 		"clients",
 		"name"
 	};
-
 	char reference[4096];
 	int val = 0;
 
@@ -104,16 +104,19 @@ test_base(int fd, struct drm_xe_query_config *config)
 
 	igt_assert(igt_debugfs_search(fd, "info", reference));
 
-	switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
-	case 48:
-		val = 3;
-		break;
-	case 57:
-		val = 4;
-		break;
+	if (!AT_LEAST_GEN(devid, 20)) {
+		switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
+		case 48:
+			val = 3;
+			break;
+		case 57:
+			val = 4;
+			break;
+		}
+
+		sprintf(reference, "vm_max_level %d", val);
+		igt_assert(igt_debugfs_search(fd, "info", reference));
 	}
-	sprintf(reference, "vm_max_level %d", val);
-	igt_assert(igt_debugfs_search(fd, "info", reference));
 
 	igt_assert(igt_debugfs_exists(fd, "gt0", O_RDONLY));
 	if (config->info[XE_QUERY_CONFIG_GT_COUNT] > 1)
-- 
2.40.1


  parent reply	other threads:[~2023-08-29 14:11 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-29 14:11 [igt-dev] [PATCH igt 0/4] Add LNL support to xe tests Lucas De Marchi
2023-08-29 14:11 ` [Intel-xe] " Lucas De Marchi
2023-08-29 14:11 ` [igt-dev] [PATCH igt 1/4] lib: Add xe_pciids.h Lucas De Marchi
2023-08-29 14:11   ` [Intel-xe] " Lucas De Marchi
2023-08-31  6:28   ` [igt-dev] " Balasubramani Vivekanandan
2023-08-31  6:28     ` Balasubramani Vivekanandan
2023-08-31  6:55     ` [igt-dev] " Balasubramani Vivekanandan
2023-08-31  6:55       ` Balasubramani Vivekanandan
2023-09-01  9:21     ` [igt-dev] " Lucas De Marchi
2023-09-01  9:21       ` Lucas De Marchi
2023-09-01 12:17       ` [igt-dev] " Vivi, Rodrigo
2023-09-01 12:17         ` Vivi, Rodrigo
2023-08-29 14:11 ` [igt-dev] [PATCH igt 2/4] lib/intel_chipset: Add Lunar Lake support Lucas De Marchi
2023-08-29 14:11   ` [Intel-xe] " Lucas De Marchi
2023-08-31  6:48   ` [igt-dev] " Balasubramani Vivekanandan
2023-08-31  6:48     ` Balasubramani Vivekanandan
2023-08-31  6:51     ` [igt-dev] " Balasubramani Vivekanandan
2023-08-31  6:51       ` Balasubramani Vivekanandan
2023-08-31 17:15     ` [igt-dev] " Matt Roper
2023-08-31 17:15       ` Matt Roper
2023-08-29 14:11 ` [igt-dev] [PATCH igt 3/4] lib/intel_device_info: Add blitter cmd info for Lunar Lake Lucas De Marchi
2023-08-29 14:11   ` [Intel-xe] " Lucas De Marchi
2023-08-30 23:48   ` [igt-dev] " Srivatsa, Anusha
2023-08-30 23:48     ` [Intel-xe] " Srivatsa, Anusha
2023-08-29 14:11 ` Lucas De Marchi [this message]
2023-08-29 14:11   ` [Intel-xe] [PATCH igt 4/4] tests/xe_debugfs: skip page table level check for Xe2 Lucas De Marchi
2023-08-30 23:50   ` [igt-dev] " Srivatsa, Anusha
2023-08-30 23:50     ` [Intel-xe] " Srivatsa, Anusha
2023-08-29 14:26 ` [igt-dev] ✗ GitLab.Pipeline: warning for Add LNL support to xe tests Patchwork
2023-08-29 14:59 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2023-08-29 15:26 ` [igt-dev] ✓ CI.xeBAT: " Patchwork
2023-08-29 15:28 ` [Intel-xe] ✗ CI.Patch_applied: failure " Patchwork
2023-08-29 21:38 ` [igt-dev] ✗ Fi.CI.IGT: " Patchwork
2023-08-30 21:07 ` [igt-dev] [Intel-xe] [PATCH igt 0/4] " Rodrigo Vivi
2023-08-30 21:07   ` Rodrigo Vivi

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