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From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Jai Luthra <j-luthra@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Sakari Ailus <sakari.ailus@linux.intel.com>,
	linux-media@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Mauro Carvalho Chehab <mchehab+samsung@kernel.org>,
	Maxime Ripard <mripard@kernel.org>,
	niklas.soderlund+renesas@ragnatech.se,
	Benoit Parrot <bparrot@ti.com>,
	Vaishnav Achath <vaishnav.a@ti.com>,
	nm@ti.com, devarsht@ti.com, a-bhatia1@ti.com,
	Martyn Welch <martyn.welch@collabora.com>,
	Julien Massot <julien.massot@collabora.com>,
	Vinod Koul <vkoul@kernel.org>
Subject: Re: [PATCH v9 13/13] media: ti: Add CSI2RX support for J721E
Date: Tue, 29 Aug 2023 18:55:13 +0300	[thread overview]
Message-ID: <20230829155513.GG6477@pendragon.ideasonboard.com> (raw)
In-Reply-To: <wgkjek77bolf5wabki7uhm6cxjy5g5z2ncoc6urr7dv5y6wnaw@yfh7ccogxfea>

Hi Jai,

(CC'ing Vinod, the maintainer of the DMA engine subsystem, for a
question below)

On Fri, Aug 18, 2023 at 03:55:06PM +0530, Jai Luthra wrote:
> On Aug 15, 2023 at 16:00:51 +0300, Tomi Valkeinen wrote:
> > On 11/08/2023 13:47, Jai Luthra wrote:
> > > From: Pratyush Yadav <p.yadav@ti.com>

[snip]

> > > +static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int count)
> > > +{
> > > +	struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq);
> > > +	struct ti_csi2rx_dma *dma = &csi->dma;
> > > +	struct ti_csi2rx_buffer *buf;
> > > +	unsigned long flags;
> > > +	int ret = 0;
> > > +
> > > +	spin_lock_irqsave(&dma->lock, flags);
> > > +	if (list_empty(&dma->queue))
> > > +		ret = -EIO;
> > > +	spin_unlock_irqrestore(&dma->lock, flags);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	dma->drain.len = csi->v_fmt.fmt.pix.sizeimage;
> > > +	dma->drain.vaddr = dma_alloc_coherent(csi->dev, dma->drain.len,
> > > +					      &dma->drain.paddr, GFP_KERNEL);
> > > +	if (!dma->drain.vaddr)
> > > +		return -ENOMEM;
> > 
> > This is still allocating a large buffer every time streaming is started (and
> > with streams support, a separate buffer for each stream?).
> > 
> > Did you check if the TI DMA can do writes to a constant address? That would
> > be the best option, as then the whole buffer allocation problem goes away.
> 
> I checked with Vignesh, the hardware can support a scenario where we 
> flush out all the data without allocating a buffer, but I couldn't find 
> a way to signal that via the current dmaengine framework APIs. Will look 
> into it further as it will be important for multi-stream support.

That would be the best option. It's not immediately apparent to me if
the DMA engine API supports such a use case.
dmaengine_prep_interleaved_dma() gives you finer grain control on the
source and destination increments, but I haven't seen a way to instruct
the DMA engine to direct writes to /dev/null (so to speak). Vinod, is
this something that is supported, or could be supported ?

> > Alternatively, can you flush the buffers with multiple one line transfers?
> > The flushing shouldn't be performance critical, so even if that's slower
> > than a normal full-frame DMA, it shouldn't matter much. And if that can be
> > done, a single probe time line-buffer allocation should do the trick.
> 
> There will be considerable overhead if we queue many DMA transactions 
> (in the order of 1000s or even 100s), which might not be okay for the 
> scenarios where we have to drain mid-stream. Will have to run some 
> experiments to see if that is worth it.
> 
> But one optimization we can for sure do is re-use a single drain buffer 
> for all the streams. We will need to ensure to re-allocate the buffer 
> for the "largest" framesize supported across the different streams at 
> stream-on time.

If you implement .device_prep_interleaved_dma() in the DMA engine driver
you could write to a single line buffer, assuming that the hardware would
support so in a generic way.

> My guess is the endpoint is not buffering a full-frame's worth of data, 
> I will also check if we can upper bound that size to something feasible.
> 
> > Other than this drain buffer topic, I think this looks fine. So, I'm going
> > to give Rb, but I do encourage you to look more into optimizing this drain
> > buffer.
> 
> Thank you!
> 
> > Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

-- 
Regards,

Laurent Pinchart

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Jai Luthra <j-luthra@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Sakari Ailus <sakari.ailus@linux.intel.com>,
	linux-media@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Mauro Carvalho Chehab <mchehab+samsung@kernel.org>,
	Maxime Ripard <mripard@kernel.org>,
	niklas.soderlund+renesas@ragnatech.se,
	Benoit Parrot <bparrot@ti.com>,
	Vaishnav Achath <vaishnav.a@ti.com>,
	nm@ti.com, devarsht@ti.com, a-bhatia1@ti.com,
	Martyn Welch <martyn.welch@collabora.com>,
	Julien Massot <julien.massot@collabora.com>,
	Vinod Koul <vkoul@kernel.org>
Subject: Re: [PATCH v9 13/13] media: ti: Add CSI2RX support for J721E
Date: Tue, 29 Aug 2023 18:55:13 +0300	[thread overview]
Message-ID: <20230829155513.GG6477@pendragon.ideasonboard.com> (raw)
In-Reply-To: <wgkjek77bolf5wabki7uhm6cxjy5g5z2ncoc6urr7dv5y6wnaw@yfh7ccogxfea>

Hi Jai,

(CC'ing Vinod, the maintainer of the DMA engine subsystem, for a
question below)

On Fri, Aug 18, 2023 at 03:55:06PM +0530, Jai Luthra wrote:
> On Aug 15, 2023 at 16:00:51 +0300, Tomi Valkeinen wrote:
> > On 11/08/2023 13:47, Jai Luthra wrote:
> > > From: Pratyush Yadav <p.yadav@ti.com>

[snip]

> > > +static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int count)
> > > +{
> > > +	struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq);
> > > +	struct ti_csi2rx_dma *dma = &csi->dma;
> > > +	struct ti_csi2rx_buffer *buf;
> > > +	unsigned long flags;
> > > +	int ret = 0;
> > > +
> > > +	spin_lock_irqsave(&dma->lock, flags);
> > > +	if (list_empty(&dma->queue))
> > > +		ret = -EIO;
> > > +	spin_unlock_irqrestore(&dma->lock, flags);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	dma->drain.len = csi->v_fmt.fmt.pix.sizeimage;
> > > +	dma->drain.vaddr = dma_alloc_coherent(csi->dev, dma->drain.len,
> > > +					      &dma->drain.paddr, GFP_KERNEL);
> > > +	if (!dma->drain.vaddr)
> > > +		return -ENOMEM;
> > 
> > This is still allocating a large buffer every time streaming is started (and
> > with streams support, a separate buffer for each stream?).
> > 
> > Did you check if the TI DMA can do writes to a constant address? That would
> > be the best option, as then the whole buffer allocation problem goes away.
> 
> I checked with Vignesh, the hardware can support a scenario where we 
> flush out all the data without allocating a buffer, but I couldn't find 
> a way to signal that via the current dmaengine framework APIs. Will look 
> into it further as it will be important for multi-stream support.

That would be the best option. It's not immediately apparent to me if
the DMA engine API supports such a use case.
dmaengine_prep_interleaved_dma() gives you finer grain control on the
source and destination increments, but I haven't seen a way to instruct
the DMA engine to direct writes to /dev/null (so to speak). Vinod, is
this something that is supported, or could be supported ?

> > Alternatively, can you flush the buffers with multiple one line transfers?
> > The flushing shouldn't be performance critical, so even if that's slower
> > than a normal full-frame DMA, it shouldn't matter much. And if that can be
> > done, a single probe time line-buffer allocation should do the trick.
> 
> There will be considerable overhead if we queue many DMA transactions 
> (in the order of 1000s or even 100s), which might not be okay for the 
> scenarios where we have to drain mid-stream. Will have to run some 
> experiments to see if that is worth it.
> 
> But one optimization we can for sure do is re-use a single drain buffer 
> for all the streams. We will need to ensure to re-allocate the buffer 
> for the "largest" framesize supported across the different streams at 
> stream-on time.

If you implement .device_prep_interleaved_dma() in the DMA engine driver
you could write to a single line buffer, assuming that the hardware would
support so in a generic way.

> My guess is the endpoint is not buffering a full-frame's worth of data, 
> I will also check if we can upper bound that size to something feasible.
> 
> > Other than this drain buffer topic, I think this looks fine. So, I'm going
> > to give Rb, but I do encourage you to look more into optimizing this drain
> > buffer.
> 
> Thank you!
> 
> > Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

-- 
Regards,

Laurent Pinchart

  reply	other threads:[~2023-08-29 15:55 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-11 10:47 [PATCH v9 00/13] CSI2RX support on J721E and AM62 Jai Luthra
2023-08-11 10:47 ` Jai Luthra
2023-08-11 10:47 ` [PATCH v9 01/13] media: dt-bindings: Make sure items in data-lanes are unique Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-11 10:47 ` [PATCH v9 02/13] media: dt-bindings: cadence-csi2rx: Add TI compatible string Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-25  3:44   ` Laurent Pinchart
2023-08-25  3:44     ` Laurent Pinchart
2023-08-11 10:47 ` [PATCH v9 03/13] media: cadence: csi2rx: Unregister v4l2 async notifier Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-11 10:47 ` [PATCH v9 04/13] media: cadence: csi2rx: Cleanup media entity properly Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-11 10:47 ` [PATCH v9 05/13] media: cadence: csi2rx: Add get_fmt and set_fmt pad ops Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-15 12:05   ` Tomi Valkeinen
2023-08-15 12:05     ` Tomi Valkeinen
2023-08-25  3:48   ` Laurent Pinchart
2023-08-25  3:48     ` Laurent Pinchart
2023-08-11 10:47 ` [PATCH v9 06/13] media: cadence: csi2rx: Configure DPHY using link freq Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-11 10:47 ` [PATCH v9 07/13] media: cadence: csi2rx: Soft reset the streams before starting capture Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-15 12:10   ` Tomi Valkeinen
2023-08-15 12:10     ` Tomi Valkeinen
2023-08-11 10:47 ` [PATCH v9 08/13] media: cadence: csi2rx: Set the STOP bit when stopping a stream Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-11 10:47 ` [PATCH v9 09/13] media: cadence: csi2rx: Fix stream data configuration Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-11 10:47 ` [PATCH v9 10/13] media: cadence: csi2rx: Populate subdev devnode Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-11 10:47 ` [PATCH v9 11/13] media: cadence: csi2rx: Add link validation Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-11 10:47 ` [PATCH v9 12/13] media: dt-bindings: Add TI J721E CSI2RX Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-11 14:00   ` Rob Herring
2023-08-11 14:00     ` Rob Herring
2023-08-11 14:54     ` Rob Herring
2023-08-11 14:54       ` Rob Herring
2023-08-11 10:47 ` [PATCH v9 13/13] media: ti: Add CSI2RX support for J721E Jai Luthra
2023-08-11 10:47   ` Jai Luthra
2023-08-15 13:00   ` Tomi Valkeinen
2023-08-15 13:00     ` Tomi Valkeinen
2023-08-18 10:25     ` Jai Luthra
2023-08-18 10:25       ` Jai Luthra
2023-08-29 15:55       ` Laurent Pinchart [this message]
2023-08-29 15:55         ` Laurent Pinchart
2023-10-04 13:51         ` Vinod Koul
2023-10-04 13:51           ` Vinod Koul
2023-10-04 20:03           ` Laurent Pinchart
2023-10-04 20:03             ` Laurent Pinchart
2023-10-05  4:10             ` Vinod Koul
2023-10-05  4:10               ` Vinod Koul
2023-10-06 10:26             ` Jai Luthra
2023-10-06 10:26               ` Jai Luthra
2023-08-29 16:44   ` Laurent Pinchart
2023-08-29 16:44     ` Laurent Pinchart
2023-10-05  8:34     ` Jai Luthra
2023-10-05  8:34       ` Jai Luthra
2023-08-24 15:18 ` [PATCH v9 00/13] CSI2RX support on J721E and AM62 Julien Massot
2023-08-24 15:18   ` Julien Massot

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