* [PATCH v5 0/6] Panel replay phase1 implementation
@ 2023-09-05 7:35 ` Animesh Manna
0 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, jouni.hogander, Animesh Manna, arun.r.murthy
Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.
These patches are basic enablement patches added on top of
existing psr framework to enable full-screen live active frame
update mode of panel replay. Panel replay also can be enabled
in selective update mode which will be enabled in a incremental
approach.
As per current design panel replay priority is higher than psr.
intel_dp->psr.panel_replay_enabled flag indicate panel replay is enabled.
intel_dp->psr.panel_replay_enabled + intel_dp->psr.psr2_enabled indicates
panel replay is enabled in selective update mode.
intel_dp->psr.panel_replay_enabled + intel_dp->psr.psr2_enabled +
intel_psr.selective_fetch enabled indicates panel replay is
enabled in selective update mode with selective fetch.
PSR replated flags remain same like before.
Note: The patches are under testing by using panel replay emulator and
panel is not avalible.
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Animesh Manna (5):
drm/panelreplay: dpcd register definition for panelreplay
drm/i915/panelreplay: Initializaton and compute config for panel
replay
drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
drm/i915/panelreplay: enable/disable panel replay
drm/i915/panelreplay: Debugfs support for panel replay
Jouni Högander (1):
drm/i915/psr: Move psr specific dpcd init into own function
.../drm/i915/display/intel_display_types.h | 15 +-
drivers/gpu/drm/i915/display/intel_dp.c | 45 ++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 269 ++++++++++++------
drivers/gpu/drm/i915/display/intel_psr.h | 7 +
include/drm/display/drm_dp.h | 18 ++
6 files changed, 257 insertions(+), 100 deletions(-)
--
2.29.0
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH v5 1/6] drm/panelreplay: dpcd register definition for panelreplay
2023-09-05 7:35 ` Animesh Manna
@ 2023-09-05 7:35 ` Animesh Manna
-1 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
Add DPCD register definition for discovering, enabling and
checking status of panel replay of the sink.
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
include/drm/display/drm_dp.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e69cece404b3..23c2a68c32a4 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -543,6 +543,10 @@
/* DFP Capability Extension */
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+#define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */
+# define DP_PANEL_REPLAY_SUPPORT (1 << 0)
+# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1)
+
/* Link Configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
@@ -716,6 +720,13 @@
#define DP_BRANCH_DEVICE_CTRL 0x1a1
# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
+#define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */
+# define DP_PANEL_REPLAY_ENABLE (1 << 0)
+# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR (1 << 3)
+# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 4)
+# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR (1 << 5)
+# define DP_PANEL_REPLAY_SU_ENABLE (1 << 6)
+
#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
@@ -1105,6 +1116,13 @@
#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
+#define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS 0x2022 /* DP 2.1 */
+# define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK (7 << 0)
+# define DP_SINK_FRAME_LOCKED_SHIFT 3
+# define DP_SINK_FRAME_LOCKED_MASK (3 << 3)
+# define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT 5
+# define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK (1 << 5)
+
/* Extended Receiver Capability: See DP_DPCD_REV for definitions */
#define DP_DP13_DPCD_REV 0x2200
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v5 1/6] drm/panelreplay: dpcd register definition for panelreplay
@ 2023-09-05 7:35 ` Animesh Manna
0 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, jouni.hogander, Animesh Manna, arun.r.murthy
Add DPCD register definition for discovering, enabling and
checking status of panel replay of the sink.
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
include/drm/display/drm_dp.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e69cece404b3..23c2a68c32a4 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -543,6 +543,10 @@
/* DFP Capability Extension */
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+#define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */
+# define DP_PANEL_REPLAY_SUPPORT (1 << 0)
+# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1)
+
/* Link Configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
@@ -716,6 +720,13 @@
#define DP_BRANCH_DEVICE_CTRL 0x1a1
# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
+#define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */
+# define DP_PANEL_REPLAY_ENABLE (1 << 0)
+# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR (1 << 3)
+# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 4)
+# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR (1 << 5)
+# define DP_PANEL_REPLAY_SU_ENABLE (1 << 6)
+
#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
@@ -1105,6 +1116,13 @@
#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
+#define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS 0x2022 /* DP 2.1 */
+# define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK (7 << 0)
+# define DP_SINK_FRAME_LOCKED_SHIFT 3
+# define DP_SINK_FRAME_LOCKED_MASK (3 << 3)
+# define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT 5
+# define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK (1 << 5)
+
/* Extended Receiver Capability: See DP_DPCD_REV for definitions */
#define DP_DP13_DPCD_REV 0x2200
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH v5 2/6] drm/i915/psr: Move psr specific dpcd init into own function
2023-09-05 7:35 ` Animesh Manna
@ 2023-09-05 7:35 ` Animesh Manna
-1 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
From: Jouni Högander <jouni.hogander@intel.com>
This patch is preparing adding panel replay specific dpcd init.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 39 +++++++++++++-----------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b9e38acc5132..24eed99e8811 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -473,27 +473,22 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
intel_dp->psr.su_y_granularity = y;
}
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv =
+ struct drm_i915_private *i915 =
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
- drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
- sizeof(intel_dp->psr_dpcd));
-
- if (!intel_dp->psr_dpcd[0])
- return;
- drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
+ drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n",
intel_dp->psr_dpcd[0]);
if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"PSR support not currently available for this panel\n");
return;
}
if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"Panel lacks power state control, PSR cannot be enabled\n");
return;
}
@@ -502,7 +497,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
intel_dp->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
- if (DISPLAY_VER(dev_priv) >= 9 &&
+ if (DISPLAY_VER(i915) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
bool y_req = intel_dp->psr_dpcd[1] &
DP_PSR2_SU_Y_COORDINATE_REQUIRED;
@@ -520,14 +515,24 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
* GTC first.
*/
intel_dp->psr.sink_psr2_support = y_req && alpm;
- drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
+ drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n",
intel_dp->psr.sink_psr2_support ? "" : "not ");
+ }
+}
- if (intel_dp->psr.sink_psr2_support) {
- intel_dp->psr.colorimetry_support =
- intel_dp_get_colorimetry_status(intel_dp);
- intel_dp_get_su_granularity(intel_dp);
- }
+void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+{
+ drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
+ sizeof(intel_dp->psr_dpcd));
+
+ if (intel_dp->psr_dpcd[0])
+ _psr_init_dpcd(intel_dp);
+ /* TODO: Add PR case here */
+
+ if (intel_dp->psr.sink_psr2_support) {
+ intel_dp->psr.colorimetry_support =
+ intel_dp_get_colorimetry_status(intel_dp);
+ intel_dp_get_su_granularity(intel_dp);
}
}
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v5 2/6] drm/i915/psr: Move psr specific dpcd init into own function
@ 2023-09-05 7:35 ` Animesh Manna
0 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula, jouni.hogander, arun.r.murthy
From: Jouni Högander <jouni.hogander@intel.com>
This patch is preparing adding panel replay specific dpcd init.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 39 +++++++++++++-----------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b9e38acc5132..24eed99e8811 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -473,27 +473,22 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
intel_dp->psr.su_y_granularity = y;
}
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv =
+ struct drm_i915_private *i915 =
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
- drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
- sizeof(intel_dp->psr_dpcd));
-
- if (!intel_dp->psr_dpcd[0])
- return;
- drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
+ drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n",
intel_dp->psr_dpcd[0]);
if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"PSR support not currently available for this panel\n");
return;
}
if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"Panel lacks power state control, PSR cannot be enabled\n");
return;
}
@@ -502,7 +497,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
intel_dp->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
- if (DISPLAY_VER(dev_priv) >= 9 &&
+ if (DISPLAY_VER(i915) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
bool y_req = intel_dp->psr_dpcd[1] &
DP_PSR2_SU_Y_COORDINATE_REQUIRED;
@@ -520,14 +515,24 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
* GTC first.
*/
intel_dp->psr.sink_psr2_support = y_req && alpm;
- drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
+ drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n",
intel_dp->psr.sink_psr2_support ? "" : "not ");
+ }
+}
- if (intel_dp->psr.sink_psr2_support) {
- intel_dp->psr.colorimetry_support =
- intel_dp_get_colorimetry_status(intel_dp);
- intel_dp_get_su_granularity(intel_dp);
- }
+void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+{
+ drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
+ sizeof(intel_dp->psr_dpcd));
+
+ if (intel_dp->psr_dpcd[0])
+ _psr_init_dpcd(intel_dp);
+ /* TODO: Add PR case here */
+
+ if (intel_dp->psr.sink_psr2_support) {
+ intel_dp->psr.colorimetry_support =
+ intel_dp_get_colorimetry_status(intel_dp);
+ intel_dp_get_su_granularity(intel_dp);
}
}
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
2023-09-05 7:35 ` Animesh Manna
@ 2023-09-05 7:35 ` Animesh Manna
-1 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
Modify existing PSR implementation to enable panel replay feature of DP 2.0
which is similar to PSR feature of EDP panel. There is different DPCD
address to check panel capability compare to PSR and vsc sdp header
is different.
v1: Initial version.
v2:
- Set source_panel_replay_support flag under HAS_PANEL_REPLAY()
condition check. [Jouni]
- Code restructured around intel_panel_replay_init
and renamed to intel_panel_replay_init_dpcd. [Jouni]
- Remove the initial code modification around has_psr2 flag. [Jouni]
- Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
enable in intel_psr_post_plane_update. [Jouni]
v3:
- Initialize both psr and panel-replay. [Jouni]
- Initialize both panel replay and psr if detected. [Jouni]
- Refactoring psr function by introducing _psr_compute_config(). [Jouni]
- Add check for !is_edp while deriving source_panel_replay_support. [Jouni]
- Enable panel replay dpcd initialization in a separate patch. [Jouni]
v4:
- HAS_PANEL_REPLAY() check not needed during sink capability check. [Jouni]
- Set either panel replay source support or psr. [Jouni]
v5:
- HAS_PANEL_REPLAY() removed and use HAS_DP20() instead. [Jouni]
- Move psr related code to intel_psr.c. [Jani]
- Reset sink_panel_replay_support flag during disconnection. [Jani]
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../drm/i915/display/intel_display_types.h | 14 +--
drivers/gpu/drm/i915/display/intel_dp.c | 45 +++++++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 96 +++++++++++++------
drivers/gpu/drm/i915/display/intel_psr.h | 7 ++
5 files changed, 118 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c21064794f32..4022d6d8281a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1202,6 +1202,7 @@ struct intel_crtc_state {
bool has_psr2;
bool enable_psr2_sel_fetch;
bool req_psr2_sdp_prior_scanline;
+ bool has_panel_replay;
bool wm_level_disabled;
u32 dc3co_exitline;
u16 su_y_granularity;
@@ -1693,6 +1694,8 @@ struct intel_psr {
bool irq_aux_error;
u16 su_w_granularity;
u16 su_y_granularity;
+ bool source_panel_replay_support;
+ bool sink_panel_replay_support;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
@@ -1980,17 +1983,6 @@ dp_to_lspcon(struct intel_dp *intel_dp)
#define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
-#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
- (intel_dp)->psr.source_support)
-
-static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
-{
- if (!intel_encoder_is_dp(encoder))
- return false;
-
- return CAN_PSR(enc_to_intel_dp(encoder));
-}
-
static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3faa68989d85..d8c151196a81 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2338,12 +2338,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- /*
- * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
- * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
- * Colorimetry Format indication.
- */
- vsc->revision = 0x5;
+ if (crtc_state->has_panel_replay) {
+ /*
+ * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+ * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+ * Encoding/Colorimetry Format indication.
+ */
+ vsc->revision = 0x7;
+ } else {
+ /*
+ * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+ * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+ * Colorimetry Format indication.
+ */
+ vsc->revision = 0x5;
+ }
+
vsc->length = 0x13;
/* DP 1.4a spec, Table 2-120 */
@@ -2452,6 +2462,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
vsc->revision = 0x4;
vsc->length = 0xe;
}
+ } else if (crtc_state->has_panel_replay) {
+ if (intel_dp->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [Panel Replay with colorimetry info] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+ vsc);
+ } else {
+ /*
+ * [Panel Replay without colorimetry info]
+ * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+ * VSC SDP supporting 3D stereo + Panel Replay.
+ */
+ vsc->revision = 0x6;
+ vsc->length = 0x10;
+ }
} else {
/*
* [PSR1]
@@ -3747,10 +3772,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
/*
- * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
- * per DP 1.4a spec.
+ * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
+ * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
+ * Encoding/Colorimetry Format as per DP 2.0 spec.
*/
- if (vsc->revision != 0x5)
+ if (vsc->revision != 0x5 || vsc->revision != 0x7)
goto out;
/* VSC SDP Payload for DB16 through DB18 */
@@ -5275,6 +5301,7 @@ intel_dp_detect(struct drm_connector *connector,
if (status == connector_status_disconnected) {
memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+ intel_dp->psr.sink_panel_replay_support = false;
if (intel_dp->is_mst) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2d1c42a5e684..65f68997281e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -43,6 +43,7 @@
#include "intel_dpio_phy.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
+#include "intel_psr.h"
#include "skl_scaler.h"
static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
@@ -383,6 +384,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+ intel_psr_compute_config(intel_dp, pipe_config, conn_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 24eed99e8811..f2209fc94125 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -171,6 +171,15 @@
* irrelevant for normal operation.
*/
+bool intel_encoder_can_psr(struct intel_encoder *encoder)
+{
+ if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST)
+ return CAN_PSR(enc_to_intel_dp(encoder)) ||
+ CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
+ else
+ return false;
+}
+
static bool psr_global_enabled(struct intel_dp *intel_dp)
{
struct intel_connector *connector = intel_dp->attached_connector;
@@ -473,6 +482,24 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
intel_dp->psr.su_y_granularity = y;
}
+static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u8 pr_dpcd = 0;
+
+ drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd);
+
+ if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Panel replay is not supported by panel\n");
+ return;
+ }
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Panel replay is supported by panel\n");
+ intel_dp->psr.sink_panel_replay_support = true;
+}
+
static void _psr_init_dpcd(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 =
@@ -522,12 +549,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
void intel_psr_init_dpcd(struct intel_dp *intel_dp)
{
+ _panel_replay_init_dpcd(intel_dp);
+
drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
sizeof(intel_dp->psr_dpcd));
if (intel_dp->psr_dpcd[0])
_psr_init_dpcd(intel_dp);
- /* TODO: Add PR case here */
if (intel_dp->psr.sink_psr2_support) {
intel_dp->psr.colorimetry_support =
@@ -1208,13 +1236,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
-void intel_psr_compute_config(struct intel_dp *intel_dp,
- struct intel_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
+static bool _psr_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
int psr_setup_time;
/*
@@ -1222,10 +1248,36 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
* So if VRR is enabled, do not enable PSR.
*/
if (crtc_state->vrr.enable)
- return;
+ return false;
if (!CAN_PSR(intel_dp))
- return;
+ return false;
+
+ psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
+ if (psr_setup_time < 0) {
+ drm_dbg_kms(&dev_priv->drm,
+ "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
+ intel_dp->psr_dpcd[1]);
+ return false;
+ }
+
+ if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
+ adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
+ drm_dbg_kms(&dev_priv->drm,
+ "PSR condition failed: PSR setup time (%d us) too long\n",
+ psr_setup_time);
+ return false;
+ }
+
+ return true;
+}
+
+void intel_psr_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
if (!psr_global_enabled(intel_dp)) {
drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
@@ -1235,7 +1287,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
if (intel_dp->psr.sink_not_reliable) {
drm_dbg_kms(&dev_priv->drm,
"PSR sink implementation is not reliable\n");
- return;
}
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
@@ -1244,23 +1295,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
- if (psr_setup_time < 0) {
- drm_dbg_kms(&dev_priv->drm,
- "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
- intel_dp->psr_dpcd[1]);
- return;
- }
-
- if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
- adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
- drm_dbg_kms(&dev_priv->drm,
- "PSR condition failed: PSR setup time (%d us) too long\n",
- psr_setup_time);
- return;
- }
+ if (CAN_PANEL_REPLAY(intel_dp))
+ crtc_state->has_panel_replay = true;
+ else
+ crtc_state->has_psr = _psr_compute_config(intel_dp, crtc_state);
- crtc_state->has_psr = true;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
@@ -2705,7 +2744,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (!HAS_PSR(dev_priv))
+ if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
return;
/*
@@ -2723,7 +2762,10 @@ void intel_psr_init(struct intel_dp *intel_dp)
return;
}
- intel_dp->psr.source_support = true;
+ if (HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp))
+ intel_dp->psr.source_panel_replay_support = true;
+ else
+ intel_dp->psr.source_support = true;
/* Set link_standby x link_off defaults */
if (DISPLAY_VER(dev_priv) < 12)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 0b95e8aa615f..1179abc354df 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -21,6 +21,13 @@ struct intel_encoder;
struct intel_plane;
struct intel_plane_state;
+#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
+ (intel_dp)->psr.source_support)
+
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
+ (intel_dp)->psr.source_panel_replay_support)
+
+bool intel_encoder_can_psr(struct intel_encoder *encoder);
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2023-09-05 7:35 ` Animesh Manna
0 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, jouni.hogander, Animesh Manna, arun.r.murthy
Modify existing PSR implementation to enable panel replay feature of DP 2.0
which is similar to PSR feature of EDP panel. There is different DPCD
address to check panel capability compare to PSR and vsc sdp header
is different.
v1: Initial version.
v2:
- Set source_panel_replay_support flag under HAS_PANEL_REPLAY()
condition check. [Jouni]
- Code restructured around intel_panel_replay_init
and renamed to intel_panel_replay_init_dpcd. [Jouni]
- Remove the initial code modification around has_psr2 flag. [Jouni]
- Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
enable in intel_psr_post_plane_update. [Jouni]
v3:
- Initialize both psr and panel-replay. [Jouni]
- Initialize both panel replay and psr if detected. [Jouni]
- Refactoring psr function by introducing _psr_compute_config(). [Jouni]
- Add check for !is_edp while deriving source_panel_replay_support. [Jouni]
- Enable panel replay dpcd initialization in a separate patch. [Jouni]
v4:
- HAS_PANEL_REPLAY() check not needed during sink capability check. [Jouni]
- Set either panel replay source support or psr. [Jouni]
v5:
- HAS_PANEL_REPLAY() removed and use HAS_DP20() instead. [Jouni]
- Move psr related code to intel_psr.c. [Jani]
- Reset sink_panel_replay_support flag during disconnection. [Jani]
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../drm/i915/display/intel_display_types.h | 14 +--
drivers/gpu/drm/i915/display/intel_dp.c | 45 +++++++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 96 +++++++++++++------
drivers/gpu/drm/i915/display/intel_psr.h | 7 ++
5 files changed, 118 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c21064794f32..4022d6d8281a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1202,6 +1202,7 @@ struct intel_crtc_state {
bool has_psr2;
bool enable_psr2_sel_fetch;
bool req_psr2_sdp_prior_scanline;
+ bool has_panel_replay;
bool wm_level_disabled;
u32 dc3co_exitline;
u16 su_y_granularity;
@@ -1693,6 +1694,8 @@ struct intel_psr {
bool irq_aux_error;
u16 su_w_granularity;
u16 su_y_granularity;
+ bool source_panel_replay_support;
+ bool sink_panel_replay_support;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
@@ -1980,17 +1983,6 @@ dp_to_lspcon(struct intel_dp *intel_dp)
#define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
-#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
- (intel_dp)->psr.source_support)
-
-static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
-{
- if (!intel_encoder_is_dp(encoder))
- return false;
-
- return CAN_PSR(enc_to_intel_dp(encoder));
-}
-
static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3faa68989d85..d8c151196a81 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2338,12 +2338,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- /*
- * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
- * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
- * Colorimetry Format indication.
- */
- vsc->revision = 0x5;
+ if (crtc_state->has_panel_replay) {
+ /*
+ * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+ * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+ * Encoding/Colorimetry Format indication.
+ */
+ vsc->revision = 0x7;
+ } else {
+ /*
+ * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+ * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+ * Colorimetry Format indication.
+ */
+ vsc->revision = 0x5;
+ }
+
vsc->length = 0x13;
/* DP 1.4a spec, Table 2-120 */
@@ -2452,6 +2462,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
vsc->revision = 0x4;
vsc->length = 0xe;
}
+ } else if (crtc_state->has_panel_replay) {
+ if (intel_dp->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [Panel Replay with colorimetry info] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+ vsc);
+ } else {
+ /*
+ * [Panel Replay without colorimetry info]
+ * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+ * VSC SDP supporting 3D stereo + Panel Replay.
+ */
+ vsc->revision = 0x6;
+ vsc->length = 0x10;
+ }
} else {
/*
* [PSR1]
@@ -3747,10 +3772,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
/*
- * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
- * per DP 1.4a spec.
+ * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
+ * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
+ * Encoding/Colorimetry Format as per DP 2.0 spec.
*/
- if (vsc->revision != 0x5)
+ if (vsc->revision != 0x5 || vsc->revision != 0x7)
goto out;
/* VSC SDP Payload for DB16 through DB18 */
@@ -5275,6 +5301,7 @@ intel_dp_detect(struct drm_connector *connector,
if (status == connector_status_disconnected) {
memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
+ intel_dp->psr.sink_panel_replay_support = false;
if (intel_dp->is_mst) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2d1c42a5e684..65f68997281e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -43,6 +43,7 @@
#include "intel_dpio_phy.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
+#include "intel_psr.h"
#include "skl_scaler.h"
static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
@@ -383,6 +384,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
+ intel_psr_compute_config(intel_dp, pipe_config, conn_state);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 24eed99e8811..f2209fc94125 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -171,6 +171,15 @@
* irrelevant for normal operation.
*/
+bool intel_encoder_can_psr(struct intel_encoder *encoder)
+{
+ if (intel_encoder_is_dp(encoder) || encoder->type == INTEL_OUTPUT_DP_MST)
+ return CAN_PSR(enc_to_intel_dp(encoder)) ||
+ CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
+ else
+ return false;
+}
+
static bool psr_global_enabled(struct intel_dp *intel_dp)
{
struct intel_connector *connector = intel_dp->attached_connector;
@@ -473,6 +482,24 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
intel_dp->psr.su_y_granularity = y;
}
+static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u8 pr_dpcd = 0;
+
+ drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd);
+
+ if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Panel replay is not supported by panel\n");
+ return;
+ }
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Panel replay is supported by panel\n");
+ intel_dp->psr.sink_panel_replay_support = true;
+}
+
static void _psr_init_dpcd(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 =
@@ -522,12 +549,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
void intel_psr_init_dpcd(struct intel_dp *intel_dp)
{
+ _panel_replay_init_dpcd(intel_dp);
+
drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
sizeof(intel_dp->psr_dpcd));
if (intel_dp->psr_dpcd[0])
_psr_init_dpcd(intel_dp);
- /* TODO: Add PR case here */
if (intel_dp->psr.sink_psr2_support) {
intel_dp->psr.colorimetry_support =
@@ -1208,13 +1236,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
-void intel_psr_compute_config(struct intel_dp *intel_dp,
- struct intel_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
+static bool _psr_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
int psr_setup_time;
/*
@@ -1222,10 +1248,36 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
* So if VRR is enabled, do not enable PSR.
*/
if (crtc_state->vrr.enable)
- return;
+ return false;
if (!CAN_PSR(intel_dp))
- return;
+ return false;
+
+ psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
+ if (psr_setup_time < 0) {
+ drm_dbg_kms(&dev_priv->drm,
+ "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
+ intel_dp->psr_dpcd[1]);
+ return false;
+ }
+
+ if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
+ adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
+ drm_dbg_kms(&dev_priv->drm,
+ "PSR condition failed: PSR setup time (%d us) too long\n",
+ psr_setup_time);
+ return false;
+ }
+
+ return true;
+}
+
+void intel_psr_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
if (!psr_global_enabled(intel_dp)) {
drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
@@ -1235,7 +1287,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
if (intel_dp->psr.sink_not_reliable) {
drm_dbg_kms(&dev_priv->drm,
"PSR sink implementation is not reliable\n");
- return;
}
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
@@ -1244,23 +1295,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
return;
}
- psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
- if (psr_setup_time < 0) {
- drm_dbg_kms(&dev_priv->drm,
- "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
- intel_dp->psr_dpcd[1]);
- return;
- }
-
- if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
- adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
- drm_dbg_kms(&dev_priv->drm,
- "PSR condition failed: PSR setup time (%d us) too long\n",
- psr_setup_time);
- return;
- }
+ if (CAN_PANEL_REPLAY(intel_dp))
+ crtc_state->has_panel_replay = true;
+ else
+ crtc_state->has_psr = _psr_compute_config(intel_dp, crtc_state);
- crtc_state->has_psr = true;
crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
@@ -2705,7 +2744,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- if (!HAS_PSR(dev_priv))
+ if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
return;
/*
@@ -2723,7 +2762,10 @@ void intel_psr_init(struct intel_dp *intel_dp)
return;
}
- intel_dp->psr.source_support = true;
+ if (HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp))
+ intel_dp->psr.source_panel_replay_support = true;
+ else
+ intel_dp->psr.source_support = true;
/* Set link_standby x link_off defaults */
if (DISPLAY_VER(dev_priv) < 12)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 0b95e8aa615f..1179abc354df 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -21,6 +21,13 @@ struct intel_encoder;
struct intel_plane;
struct intel_plane_state;
+#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
+ (intel_dp)->psr.source_support)
+
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
+ (intel_dp)->psr.source_panel_replay_support)
+
+bool intel_encoder_can_psr(struct intel_encoder *encoder);
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
2023-09-05 7:35 ` Animesh Manna
@ 2023-09-05 11:00 ` kernel test robot
-1 siblings, 0 replies; 27+ messages in thread
From: kernel test robot @ 2023-09-05 11:00 UTC (permalink / raw)
To: Animesh Manna, intel-gfx, dri-devel; +Cc: jani.nikula, llvm, oe-kbuild-all
Hi Animesh,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230905-154811
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230905073551.958368-4-animesh.manna%40intel.com
patch subject: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
config: i386-randconfig-r036-20230905 (https://download.01.org/0day-ci/archive/20230905/202309051831.AMUjJOcB-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230905/202309051831.AMUjJOcB-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309051831.AMUjJOcB-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_dp.c:3779:27: warning: overlapping comparisons always evaluate to true [-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +3779 drivers/gpu/drm/i915/display/intel_dp.c
3754
3755 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3756 struct dp_sdp *sdp, size_t size)
3757 {
3758 size_t length = sizeof(struct dp_sdp);
3759
3760 if (size < length)
3761 return -ENOSPC;
3762
3763 memset(sdp, 0, size);
3764
3765 /*
3766 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3767 * VSC SDP Header Bytes
3768 */
3769 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3770 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3771 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3772 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3773
3774 /*
3775 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
3776 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
3777 * Encoding/Colorimetry Format as per DP 2.0 spec.
3778 */
> 3779 if (vsc->revision != 0x5 || vsc->revision != 0x7)
3780 goto out;
3781
3782 /* VSC SDP Payload for DB16 through DB18 */
3783 /* Pixel Encoding and Colorimetry Formats */
3784 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3785 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3786
3787 switch (vsc->bpc) {
3788 case 6:
3789 /* 6bpc: 0x0 */
3790 break;
3791 case 8:
3792 sdp->db[17] = 0x1; /* DB17[3:0] */
3793 break;
3794 case 10:
3795 sdp->db[17] = 0x2;
3796 break;
3797 case 12:
3798 sdp->db[17] = 0x3;
3799 break;
3800 case 16:
3801 sdp->db[17] = 0x4;
3802 break;
3803 default:
3804 MISSING_CASE(vsc->bpc);
3805 break;
3806 }
3807 /* Dynamic Range and Component Bit Depth */
3808 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3809 sdp->db[17] |= 0x80; /* DB17[7] */
3810
3811 /* Content Type */
3812 sdp->db[18] = vsc->content_type & 0x7;
3813
3814 out:
3815 return length;
3816 }
3817
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2023-09-05 11:00 ` kernel test robot
0 siblings, 0 replies; 27+ messages in thread
From: kernel test robot @ 2023-09-05 11:00 UTC (permalink / raw)
To: Animesh Manna, intel-gfx, dri-devel; +Cc: llvm, oe-kbuild-all, jani.nikula
Hi Animesh,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230905-154811
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230905073551.958368-4-animesh.manna%40intel.com
patch subject: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
config: i386-randconfig-r036-20230905 (https://download.01.org/0day-ci/archive/20230905/202309051831.AMUjJOcB-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230905/202309051831.AMUjJOcB-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309051831.AMUjJOcB-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_dp.c:3779:27: warning: overlapping comparisons always evaluate to true [-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +3779 drivers/gpu/drm/i915/display/intel_dp.c
3754
3755 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3756 struct dp_sdp *sdp, size_t size)
3757 {
3758 size_t length = sizeof(struct dp_sdp);
3759
3760 if (size < length)
3761 return -ENOSPC;
3762
3763 memset(sdp, 0, size);
3764
3765 /*
3766 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3767 * VSC SDP Header Bytes
3768 */
3769 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3770 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3771 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3772 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3773
3774 /*
3775 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
3776 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
3777 * Encoding/Colorimetry Format as per DP 2.0 spec.
3778 */
> 3779 if (vsc->revision != 0x5 || vsc->revision != 0x7)
3780 goto out;
3781
3782 /* VSC SDP Payload for DB16 through DB18 */
3783 /* Pixel Encoding and Colorimetry Formats */
3784 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3785 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3786
3787 switch (vsc->bpc) {
3788 case 6:
3789 /* 6bpc: 0x0 */
3790 break;
3791 case 8:
3792 sdp->db[17] = 0x1; /* DB17[3:0] */
3793 break;
3794 case 10:
3795 sdp->db[17] = 0x2;
3796 break;
3797 case 12:
3798 sdp->db[17] = 0x3;
3799 break;
3800 case 16:
3801 sdp->db[17] = 0x4;
3802 break;
3803 default:
3804 MISSING_CASE(vsc->bpc);
3805 break;
3806 }
3807 /* Dynamic Range and Component Bit Depth */
3808 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3809 sdp->db[17] |= 0x80; /* DB17[7] */
3810
3811 /* Content Type */
3812 sdp->db[18] = vsc->content_type & 0x7;
3813
3814 out:
3815 return length;
3816 }
3817
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
2023-09-05 7:35 ` Animesh Manna
@ 2023-09-05 11:42 ` kernel test robot
-1 siblings, 0 replies; 27+ messages in thread
From: kernel test robot @ 2023-09-05 11:42 UTC (permalink / raw)
To: Animesh Manna, intel-gfx, dri-devel; +Cc: jani.nikula, llvm, oe-kbuild-all
Hi Animesh,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230905-154811
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230905073551.958368-4-animesh.manna%40intel.com
patch subject: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
config: i386-randconfig-003-20230905 (https://download.01.org/0day-ci/archive/20230905/202309051920.FD7yiD3K-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230905/202309051920.FD7yiD3K-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309051920.FD7yiD3K-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_dp.c:3779:27: error: overlapping comparisons always evaluate to true [-Werror,-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
vim +3779 drivers/gpu/drm/i915/display/intel_dp.c
3754
3755 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3756 struct dp_sdp *sdp, size_t size)
3757 {
3758 size_t length = sizeof(struct dp_sdp);
3759
3760 if (size < length)
3761 return -ENOSPC;
3762
3763 memset(sdp, 0, size);
3764
3765 /*
3766 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3767 * VSC SDP Header Bytes
3768 */
3769 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3770 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3771 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3772 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3773
3774 /*
3775 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
3776 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
3777 * Encoding/Colorimetry Format as per DP 2.0 spec.
3778 */
> 3779 if (vsc->revision != 0x5 || vsc->revision != 0x7)
3780 goto out;
3781
3782 /* VSC SDP Payload for DB16 through DB18 */
3783 /* Pixel Encoding and Colorimetry Formats */
3784 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3785 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3786
3787 switch (vsc->bpc) {
3788 case 6:
3789 /* 6bpc: 0x0 */
3790 break;
3791 case 8:
3792 sdp->db[17] = 0x1; /* DB17[3:0] */
3793 break;
3794 case 10:
3795 sdp->db[17] = 0x2;
3796 break;
3797 case 12:
3798 sdp->db[17] = 0x3;
3799 break;
3800 case 16:
3801 sdp->db[17] = 0x4;
3802 break;
3803 default:
3804 MISSING_CASE(vsc->bpc);
3805 break;
3806 }
3807 /* Dynamic Range and Component Bit Depth */
3808 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3809 sdp->db[17] |= 0x80; /* DB17[7] */
3810
3811 /* Content Type */
3812 sdp->db[18] = vsc->content_type & 0x7;
3813
3814 out:
3815 return length;
3816 }
3817
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2023-09-05 11:42 ` kernel test robot
0 siblings, 0 replies; 27+ messages in thread
From: kernel test robot @ 2023-09-05 11:42 UTC (permalink / raw)
To: Animesh Manna, intel-gfx, dri-devel; +Cc: llvm, oe-kbuild-all, jani.nikula
Hi Animesh,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-tip/drm-tip]
url: https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230905-154811
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230905073551.958368-4-animesh.manna%40intel.com
patch subject: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
config: i386-randconfig-003-20230905 (https://download.01.org/0day-ci/archive/20230905/202309051920.FD7yiD3K-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230905/202309051920.FD7yiD3K-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309051920.FD7yiD3K-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_dp.c:3779:27: error: overlapping comparisons always evaluate to true [-Werror,-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
vim +3779 drivers/gpu/drm/i915/display/intel_dp.c
3754
3755 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3756 struct dp_sdp *sdp, size_t size)
3757 {
3758 size_t length = sizeof(struct dp_sdp);
3759
3760 if (size < length)
3761 return -ENOSPC;
3762
3763 memset(sdp, 0, size);
3764
3765 /*
3766 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3767 * VSC SDP Header Bytes
3768 */
3769 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3770 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3771 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3772 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3773
3774 /*
3775 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
3776 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
3777 * Encoding/Colorimetry Format as per DP 2.0 spec.
3778 */
> 3779 if (vsc->revision != 0x5 || vsc->revision != 0x7)
3780 goto out;
3781
3782 /* VSC SDP Payload for DB16 through DB18 */
3783 /* Pixel Encoding and Colorimetry Formats */
3784 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3785 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3786
3787 switch (vsc->bpc) {
3788 case 6:
3789 /* 6bpc: 0x0 */
3790 break;
3791 case 8:
3792 sdp->db[17] = 0x1; /* DB17[3:0] */
3793 break;
3794 case 10:
3795 sdp->db[17] = 0x2;
3796 break;
3797 case 12:
3798 sdp->db[17] = 0x3;
3799 break;
3800 case 16:
3801 sdp->db[17] = 0x4;
3802 break;
3803 default:
3804 MISSING_CASE(vsc->bpc);
3805 break;
3806 }
3807 /* Dynamic Range and Component Bit Depth */
3808 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3809 sdp->db[17] |= 0x80; /* DB17[7] */
3810
3811 /* Content Type */
3812 sdp->db[18] = vsc->content_type & 0x7;
3813
3814 out:
3815 return length;
3816 }
3817
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
2023-09-05 7:35 ` Animesh Manna
(?)
@ 2023-09-06 9:00 ` Dan Carpenter
-1 siblings, 0 replies; 27+ messages in thread
From: Dan Carpenter @ 2023-09-06 9:00 UTC (permalink / raw)
To: oe-kbuild, Animesh Manna, intel-gfx, dri-devel; +Cc: jani.nikula, oe-kbuild-all
Hi Animesh,
kernel test robot noticed the following build warnings:
url: https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230905-154811
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230905073551.958368-4-animesh.manna%40intel.com
patch subject: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
config: i386-randconfig-141-20230906 (https://download.01.org/0day-ci/archive/20230906/202309060644.uWp5zW4i-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230906/202309060644.uWp5zW4i-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202309060644.uWp5zW4i-lkp@intel.com/
smatch warnings:
drivers/gpu/drm/i915/display/intel_dp.c:3779 intel_dp_vsc_sdp_pack() warn: was && intended here instead of ||?
vim +3779 drivers/gpu/drm/i915/display/intel_dp.c
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3755 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3756 struct dp_sdp *sdp, size_t size)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3757 {
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3758 size_t length = sizeof(struct dp_sdp);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3759
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3760 if (size < length)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3761 return -ENOSPC;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3762
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3763 memset(sdp, 0, size);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3764
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3765 /*
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3766 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3767 * VSC SDP Header Bytes
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3768 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3769 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3770 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3771 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3772 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3773
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3774 /*
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 3775 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 3776 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 3777 * Encoding/Colorimetry Format as per DP 2.0 spec.
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3778 */
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 @3779 if (vsc->revision != 0x5 || vsc->revision != 0x7)
This changes the rest of the function into a no-op. Ideally this sort
bug would be caught in testing.
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3780 goto out;
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3781
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3782 /* VSC SDP Payload for DB16 through DB18 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3783 /* Pixel Encoding and Colorimetry Formats */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3784 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3785 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3786
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3787 switch (vsc->bpc) {
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3788 case 6:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3789 /* 6bpc: 0x0 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3790 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3791 case 8:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3792 sdp->db[17] = 0x1; /* DB17[3:0] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3793 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3794 case 10:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3795 sdp->db[17] = 0x2;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3796 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3797 case 12:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3798 sdp->db[17] = 0x3;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3799 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3800 case 16:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3801 sdp->db[17] = 0x4;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3802 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3803 default:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3804 MISSING_CASE(vsc->bpc);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3805 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3806 }
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3807 /* Dynamic Range and Component Bit Depth */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3808 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3809 sdp->db[17] |= 0x80; /* DB17[7] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3810
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3811 /* Content Type */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3812 sdp->db[18] = vsc->content_type & 0x7;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3813
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3814 out:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3815 return length;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3816 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2023-09-06 9:00 ` Dan Carpenter
0 siblings, 0 replies; 27+ messages in thread
From: Dan Carpenter @ 2023-09-06 9:00 UTC (permalink / raw)
To: oe-kbuild, Animesh Manna, intel-gfx, dri-devel
Cc: jani.nikula, lkp, oe-kbuild-all
Hi Animesh,
kernel test robot noticed the following build warnings:
url: https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230905-154811
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230905073551.958368-4-animesh.manna%40intel.com
patch subject: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
config: i386-randconfig-141-20230906 (https://download.01.org/0day-ci/archive/20230906/202309060644.uWp5zW4i-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230906/202309060644.uWp5zW4i-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202309060644.uWp5zW4i-lkp@intel.com/
smatch warnings:
drivers/gpu/drm/i915/display/intel_dp.c:3779 intel_dp_vsc_sdp_pack() warn: was && intended here instead of ||?
vim +3779 drivers/gpu/drm/i915/display/intel_dp.c
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3755 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3756 struct dp_sdp *sdp, size_t size)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3757 {
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3758 size_t length = sizeof(struct dp_sdp);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3759
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3760 if (size < length)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3761 return -ENOSPC;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3762
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3763 memset(sdp, 0, size);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3764
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3765 /*
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3766 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3767 * VSC SDP Header Bytes
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3768 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3769 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3770 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3771 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3772 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3773
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3774 /*
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 3775 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 3776 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 3777 * Encoding/Colorimetry Format as per DP 2.0 spec.
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3778 */
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 @3779 if (vsc->revision != 0x5 || vsc->revision != 0x7)
This changes the rest of the function into a no-op. Ideally this sort
bug would be caught in testing.
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3780 goto out;
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3781
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3782 /* VSC SDP Payload for DB16 through DB18 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3783 /* Pixel Encoding and Colorimetry Formats */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3784 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3785 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3786
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3787 switch (vsc->bpc) {
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3788 case 6:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3789 /* 6bpc: 0x0 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3790 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3791 case 8:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3792 sdp->db[17] = 0x1; /* DB17[3:0] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3793 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3794 case 10:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3795 sdp->db[17] = 0x2;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3796 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3797 case 12:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3798 sdp->db[17] = 0x3;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3799 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3800 case 16:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3801 sdp->db[17] = 0x4;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3802 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3803 default:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3804 MISSING_CASE(vsc->bpc);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3805 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3806 }
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3807 /* Dynamic Range and Component Bit Depth */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3808 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3809 sdp->db[17] |= 0x80; /* DB17[7] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3810
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3811 /* Content Type */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3812 sdp->db[18] = vsc->content_type & 0x7;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3813
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3814 out:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3815 return length;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3816 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2023-09-06 9:00 ` Dan Carpenter
0 siblings, 0 replies; 27+ messages in thread
From: Dan Carpenter @ 2023-09-06 9:00 UTC (permalink / raw)
To: oe-kbuild, Animesh Manna, intel-gfx, dri-devel
Cc: lkp, oe-kbuild-all, jani.nikula
Hi Animesh,
kernel test robot noticed the following build warnings:
url: https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230905-154811
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link: https://lore.kernel.org/r/20230905073551.958368-4-animesh.manna%40intel.com
patch subject: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
config: i386-randconfig-141-20230906 (https://download.01.org/0day-ci/archive/20230906/202309060644.uWp5zW4i-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230906/202309060644.uWp5zW4i-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202309060644.uWp5zW4i-lkp@intel.com/
smatch warnings:
drivers/gpu/drm/i915/display/intel_dp.c:3779 intel_dp_vsc_sdp_pack() warn: was && intended here instead of ||?
vim +3779 drivers/gpu/drm/i915/display/intel_dp.c
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3755 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3756 struct dp_sdp *sdp, size_t size)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3757 {
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3758 size_t length = sizeof(struct dp_sdp);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3759
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3760 if (size < length)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3761 return -ENOSPC;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3762
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3763 memset(sdp, 0, size);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3764
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3765 /*
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3766 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3767 * VSC SDP Header Bytes
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3768 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3769 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3770 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3771 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3772 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3773
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3774 /*
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 3775 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 3776 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 3777 * Encoding/Colorimetry Format as per DP 2.0 spec.
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3778 */
4dd2d4a2ffcae4 Animesh Manna 2023-09-05 @3779 if (vsc->revision != 0x5 || vsc->revision != 0x7)
This changes the rest of the function into a no-op. Ideally this sort
bug would be caught in testing.
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3780 goto out;
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3781
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3782 /* VSC SDP Payload for DB16 through DB18 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3783 /* Pixel Encoding and Colorimetry Formats */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3784 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3785 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3786
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3787 switch (vsc->bpc) {
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3788 case 6:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3789 /* 6bpc: 0x0 */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3790 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3791 case 8:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3792 sdp->db[17] = 0x1; /* DB17[3:0] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3793 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3794 case 10:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3795 sdp->db[17] = 0x2;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3796 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3797 case 12:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3798 sdp->db[17] = 0x3;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3799 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3800 case 16:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3801 sdp->db[17] = 0x4;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3802 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3803 default:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3804 MISSING_CASE(vsc->bpc);
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3805 break;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3806 }
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3807 /* Dynamic Range and Component Bit Depth */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3808 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3809 sdp->db[17] |= 0x80; /* DB17[7] */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3810
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3811 /* Content Type */
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3812 sdp->db[18] = vsc->content_type & 0x7;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3813
cafac5a9836199 Gwan-gyeong Mun 2020-05-14 3814 out:
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3815 return length;
03c761b00c87d6 Gwan-gyeong Mun 2020-02-11 3816 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
2023-09-05 7:35 ` Animesh Manna
@ 2023-09-11 6:59 ` Hogander, Jouni
-1 siblings, 0 replies; 27+ messages in thread
From: Hogander, Jouni @ 2023-09-11 6:59 UTC (permalink / raw)
To: dri-devel@lists.freedesktop.org, Manna, Animesh,
intel-gfx@lists.freedesktop.org
Cc: Nikula, Jani
On Tue, 2023-09-05 at 13:05 +0530, Animesh Manna wrote:
> Modify existing PSR implementation to enable panel replay feature of
> DP 2.0
> which is similar to PSR feature of EDP panel. There is different DPCD
> address to check panel capability compare to PSR and vsc sdp header
> is different.
>
> v1: Initial version.
> v2:
> - Set source_panel_replay_support flag under HAS_PANEL_REPLAY()
> condition check. [Jouni]
> - Code restructured around intel_panel_replay_init
> and renamed to intel_panel_replay_init_dpcd. [Jouni]
> - Remove the initial code modification around has_psr2 flag. [Jouni]
> - Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
> enable in intel_psr_post_plane_update. [Jouni]
> v3:
> - Initialize both psr and panel-replay. [Jouni]
> - Initialize both panel replay and psr if detected. [Jouni]
> - Refactoring psr function by introducing _psr_compute_config().
> [Jouni]
> - Add check for !is_edp while deriving source_panel_replay_support.
> [Jouni]
> - Enable panel replay dpcd initialization in a separate patch.
> [Jouni]
>
> v4:
> - HAS_PANEL_REPLAY() check not needed during sink capability check.
> [Jouni]
> - Set either panel replay source support or psr. [Jouni]
>
> v5:
> - HAS_PANEL_REPLAY() removed and use HAS_DP20() instead. [Jouni]
> - Move psr related code to intel_psr.c. [Jani]
> - Reset sink_panel_replay_support flag during disconnection. [Jani]
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 14 +--
> drivers/gpu/drm/i915/display/intel_dp.c | 45 +++++++--
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +
> drivers/gpu/drm/i915/display/intel_psr.c | 96 +++++++++++++----
> --
> drivers/gpu/drm/i915/display/intel_psr.h | 7 ++
> 5 files changed, 118 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c21064794f32..4022d6d8281a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1202,6 +1202,7 @@ struct intel_crtc_state {
> bool has_psr2;
> bool enable_psr2_sel_fetch;
> bool req_psr2_sdp_prior_scanline;
> + bool has_panel_replay;
> bool wm_level_disabled;
> u32 dc3co_exitline;
> u16 su_y_granularity;
> @@ -1693,6 +1694,8 @@ struct intel_psr {
> bool irq_aux_error;
> u16 su_w_granularity;
> u16 su_y_granularity;
> + bool source_panel_replay_support;
> + bool sink_panel_replay_support;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> struct delayed_work dc3co_work;
> @@ -1980,17 +1983,6 @@ dp_to_lspcon(struct intel_dp *intel_dp)
>
> #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)-
> >base.base.dev)
>
> -#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> - (intel_dp)->psr.source_support)
> -
> -static inline bool intel_encoder_can_psr(struct intel_encoder
> *encoder)
> -{
> - if (!intel_encoder_is_dp(encoder))
> - return false;
> -
> - return CAN_PSR(enc_to_intel_dp(encoder));
> -}
> -
> static inline struct intel_digital_port *
> hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3faa68989d85..d8c151196a81 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2338,12 +2338,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> >uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - /*
> - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> - * Colorimetry Format indication.
> - */
> - vsc->revision = 0x5;
> + if (crtc_state->has_panel_replay) {
> + /*
> + * Prepare VSC Header for SU as per DP 2.0 spec,
> Table 2-223
> + * VSC SDP supporting 3D stereo, Panel Replay, and
> Pixel
> + * Encoding/Colorimetry Format indication.
> + */
> + vsc->revision = 0x7;
> + } else {
> + /*
> + * Prepare VSC Header for SU as per DP 1.4 spec,
> Table 2-118
> + * VSC SDP supporting 3D stereo, PSR2, and Pixel
> Encoding/
> + * Colorimetry Format indication.
> + */
> + vsc->revision = 0x5;
> + }
> +
> vsc->length = 0x13;
>
> /* DP 1.4a spec, Table 2-120 */
> @@ -2452,6 +2462,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
> vsc->revision = 0x4;
> vsc->length = 0xe;
> }
> + } else if (crtc_state->has_panel_replay) {
> + if (intel_dp->psr.colorimetry_support &&
> + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> + /* [Panel Replay with colorimetry info] */
> + intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> + vsc);
> + } else {
> + /*
> + * [Panel Replay without colorimetry info]
> + * Prepare VSC Header for SU as per DP 2.0
> spec, Table 2-223
> + * VSC SDP supporting 3D stereo + Panel
> Replay.
> + */
> + vsc->revision = 0x6;
> + vsc->length = 0x10;
> + }
> } else {
> /*
> * [PSR1]
> @@ -3747,10 +3772,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const
> struct drm_dp_vsc_sdp *vsc,
> sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data
> Bytes */
>
> /*
> - * Only revision 0x5 supports Pixel Encoding/Colorimetry
> Format as
> - * per DP 1.4a spec.
> + * Other than revision 0x5 which supports Pixel
> Encoding/Colorimetry
> + * Format as per DP 1.4a spec, revision 0x7 also supports
> Pixel
> + * Encoding/Colorimetry Format as per DP 2.0 spec.
> */
> - if (vsc->revision != 0x5)
> + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> goto out;
>
> /* VSC SDP Payload for DB16 through DB18 */
> @@ -5275,6 +5301,7 @@ intel_dp_detect(struct drm_connector
> *connector,
> if (status == connector_status_disconnected) {
> memset(&intel_dp->compliance, 0, sizeof(intel_dp-
> >compliance));
> memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp-
> >dsc_dpcd));
> + intel_dp->psr.sink_panel_replay_support = false;
>
> if (intel_dp->is_mst) {
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2d1c42a5e684..65f68997281e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -43,6 +43,7 @@
> #include "intel_dpio_phy.h"
> #include "intel_hdcp.h"
> #include "intel_hotplug.h"
> +#include "intel_psr.h"
> #include "skl_scaler.h"
>
> static int intel_dp_mst_check_constraints(struct drm_i915_private
> *i915, int bpp,
> @@ -383,6 +384,8 @@ static int intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
>
> intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>
> + intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 24eed99e8811..f2209fc94125 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -171,6 +171,15 @@
> * irrelevant for normal operation.
> */
>
> +bool intel_encoder_can_psr(struct intel_encoder *encoder)
> +{
> + if (intel_encoder_is_dp(encoder) || encoder->type ==
> INTEL_OUTPUT_DP_MST)
> + return CAN_PSR(enc_to_intel_dp(encoder)) ||
> + CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
> + else
> + return false;
> +}
> +
> static bool psr_global_enabled(struct intel_dp *intel_dp)
> {
> struct intel_connector *connector = intel_dp-
> >attached_connector;
> @@ -473,6 +482,24 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
> intel_dp->psr.su_y_granularity = y;
> }
>
> +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u8 pr_dpcd = 0;
> +
> + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> &pr_dpcd);
> +
> + if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Panel replay is not supported by
> panel\n");
> + return;
> + }
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "Panel replay is supported by panel\n");
> + intel_dp->psr.sink_panel_replay_support = true;
> +}
> +
> static void _psr_init_dpcd(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *i915 =
> @@ -522,12 +549,13 @@ static void _psr_init_dpcd(struct intel_dp
> *intel_dp)
>
> void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> {
> + _panel_replay_init_dpcd(intel_dp);
> +
> drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> >psr_dpcd,
> sizeof(intel_dp->psr_dpcd));
>
> if (intel_dp->psr_dpcd[0])
> _psr_init_dpcd(intel_dp);
> - /* TODO: Add PR case here */
>
> if (intel_dp->psr.sink_psr2_support) {
> intel_dp->psr.colorimetry_support =
> @@ -1208,13 +1236,11 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> -void intel_psr_compute_config(struct intel_dp *intel_dp,
> - struct intel_crtc_state *crtc_state,
> - struct drm_connector_state *conn_state)
> +static bool _psr_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> int psr_setup_time;
>
> /*
> @@ -1222,10 +1248,36 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> * So if VRR is enabled, do not enable PSR.
> */
> if (crtc_state->vrr.enable)
> - return;
> + return false;
>
> if (!CAN_PSR(intel_dp))
> - return;
> + return false;
> +
> + psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> + if (psr_setup_time < 0) {
> + drm_dbg_kms(&dev_priv->drm,
> + "PSR condition failed: Invalid PSR setup
> time (0x%02x)\n",
> + intel_dp->psr_dpcd[1]);
> + return false;
> + }
> +
> + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay
> - 1) {
> + drm_dbg_kms(&dev_priv->drm,
> + "PSR condition failed: PSR setup time (%d
> us) too long\n",
> + psr_setup_time);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +void intel_psr_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
>
> if (!psr_global_enabled(intel_dp)) {
> drm_dbg_kms(&dev_priv->drm, "PSR disabled by
> flag\n");
> @@ -1235,7 +1287,6 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> if (intel_dp->psr.sink_not_reliable) {
> drm_dbg_kms(&dev_priv->drm,
> "PSR sink implementation is not
> reliable\n");
> - return;
You should not remove this return here?
BR,
Jouni Högander
> }
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -1244,23 +1295,11 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> return;
> }
>
> - psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> - if (psr_setup_time < 0) {
> - drm_dbg_kms(&dev_priv->drm,
> - "PSR condition failed: Invalid PSR setup
> time (0x%02x)\n",
> - intel_dp->psr_dpcd[1]);
> - return;
> - }
> -
> - if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> - adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay
> - 1) {
> - drm_dbg_kms(&dev_priv->drm,
> - "PSR condition failed: PSR setup time (%d
> us) too long\n",
> - psr_setup_time);
> - return;
> - }
> + if (CAN_PANEL_REPLAY(intel_dp))
> + crtc_state->has_panel_replay = true;
> + else
> + crtc_state->has_psr = _psr_compute_config(intel_dp,
> crtc_state);
>
> - crtc_state->has_psr = true;
> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> crtc_state);
>
> crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> @@ -2705,7 +2744,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - if (!HAS_PSR(dev_priv))
> + if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
> return;
>
> /*
> @@ -2723,7 +2762,10 @@ void intel_psr_init(struct intel_dp *intel_dp)
> return;
> }
>
> - intel_dp->psr.source_support = true;
> + if (HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp))
> + intel_dp->psr.source_panel_replay_support = true;
> + else
> + intel_dp->psr.source_support = true;
>
> /* Set link_standby x link_off defaults */
> if (DISPLAY_VER(dev_priv) < 12)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 0b95e8aa615f..1179abc354df 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -21,6 +21,13 @@ struct intel_encoder;
> struct intel_plane;
> struct intel_plane_state;
>
> +#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> + (intel_dp)->psr.source_support)
> +
> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> + (intel_dp)-
> >psr.source_panel_replay_support)
> +
> +bool intel_encoder_can_psr(struct intel_encoder *encoder);
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH v5 3/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2023-09-11 6:59 ` Hogander, Jouni
0 siblings, 0 replies; 27+ messages in thread
From: Hogander, Jouni @ 2023-09-11 6:59 UTC (permalink / raw)
To: dri-devel@lists.freedesktop.org, Manna, Animesh,
intel-gfx@lists.freedesktop.org
Cc: Nikula, Jani, Murthy, Arun R
On Tue, 2023-09-05 at 13:05 +0530, Animesh Manna wrote:
> Modify existing PSR implementation to enable panel replay feature of
> DP 2.0
> which is similar to PSR feature of EDP panel. There is different DPCD
> address to check panel capability compare to PSR and vsc sdp header
> is different.
>
> v1: Initial version.
> v2:
> - Set source_panel_replay_support flag under HAS_PANEL_REPLAY()
> condition check. [Jouni]
> - Code restructured around intel_panel_replay_init
> and renamed to intel_panel_replay_init_dpcd. [Jouni]
> - Remove the initial code modification around has_psr2 flag. [Jouni]
> - Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
> enable in intel_psr_post_plane_update. [Jouni]
> v3:
> - Initialize both psr and panel-replay. [Jouni]
> - Initialize both panel replay and psr if detected. [Jouni]
> - Refactoring psr function by introducing _psr_compute_config().
> [Jouni]
> - Add check for !is_edp while deriving source_panel_replay_support.
> [Jouni]
> - Enable panel replay dpcd initialization in a separate patch.
> [Jouni]
>
> v4:
> - HAS_PANEL_REPLAY() check not needed during sink capability check.
> [Jouni]
> - Set either panel replay source support or psr. [Jouni]
>
> v5:
> - HAS_PANEL_REPLAY() removed and use HAS_DP20() instead. [Jouni]
> - Move psr related code to intel_psr.c. [Jani]
> - Reset sink_panel_replay_support flag during disconnection. [Jani]
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 14 +--
> drivers/gpu/drm/i915/display/intel_dp.c | 45 +++++++--
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +
> drivers/gpu/drm/i915/display/intel_psr.c | 96 +++++++++++++----
> --
> drivers/gpu/drm/i915/display/intel_psr.h | 7 ++
> 5 files changed, 118 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c21064794f32..4022d6d8281a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1202,6 +1202,7 @@ struct intel_crtc_state {
> bool has_psr2;
> bool enable_psr2_sel_fetch;
> bool req_psr2_sdp_prior_scanline;
> + bool has_panel_replay;
> bool wm_level_disabled;
> u32 dc3co_exitline;
> u16 su_y_granularity;
> @@ -1693,6 +1694,8 @@ struct intel_psr {
> bool irq_aux_error;
> u16 su_w_granularity;
> u16 su_y_granularity;
> + bool source_panel_replay_support;
> + bool sink_panel_replay_support;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> struct delayed_work dc3co_work;
> @@ -1980,17 +1983,6 @@ dp_to_lspcon(struct intel_dp *intel_dp)
>
> #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)-
> >base.base.dev)
>
> -#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> - (intel_dp)->psr.source_support)
> -
> -static inline bool intel_encoder_can_psr(struct intel_encoder
> *encoder)
> -{
> - if (!intel_encoder_is_dp(encoder))
> - return false;
> -
> - return CAN_PSR(enc_to_intel_dp(encoder));
> -}
> -
> static inline struct intel_digital_port *
> hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3faa68989d85..d8c151196a81 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2338,12 +2338,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> struct intel_crtc *crtc = to_intel_crtc(crtc_state-
> >uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - /*
> - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> - * Colorimetry Format indication.
> - */
> - vsc->revision = 0x5;
> + if (crtc_state->has_panel_replay) {
> + /*
> + * Prepare VSC Header for SU as per DP 2.0 spec,
> Table 2-223
> + * VSC SDP supporting 3D stereo, Panel Replay, and
> Pixel
> + * Encoding/Colorimetry Format indication.
> + */
> + vsc->revision = 0x7;
> + } else {
> + /*
> + * Prepare VSC Header for SU as per DP 1.4 spec,
> Table 2-118
> + * VSC SDP supporting 3D stereo, PSR2, and Pixel
> Encoding/
> + * Colorimetry Format indication.
> + */
> + vsc->revision = 0x5;
> + }
> +
> vsc->length = 0x13;
>
> /* DP 1.4a spec, Table 2-120 */
> @@ -2452,6 +2462,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
> vsc->revision = 0x4;
> vsc->length = 0xe;
> }
> + } else if (crtc_state->has_panel_replay) {
> + if (intel_dp->psr.colorimetry_support &&
> + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> + /* [Panel Replay with colorimetry info] */
> + intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> + vsc);
> + } else {
> + /*
> + * [Panel Replay without colorimetry info]
> + * Prepare VSC Header for SU as per DP 2.0
> spec, Table 2-223
> + * VSC SDP supporting 3D stereo + Panel
> Replay.
> + */
> + vsc->revision = 0x6;
> + vsc->length = 0x10;
> + }
> } else {
> /*
> * [PSR1]
> @@ -3747,10 +3772,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const
> struct drm_dp_vsc_sdp *vsc,
> sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data
> Bytes */
>
> /*
> - * Only revision 0x5 supports Pixel Encoding/Colorimetry
> Format as
> - * per DP 1.4a spec.
> + * Other than revision 0x5 which supports Pixel
> Encoding/Colorimetry
> + * Format as per DP 1.4a spec, revision 0x7 also supports
> Pixel
> + * Encoding/Colorimetry Format as per DP 2.0 spec.
> */
> - if (vsc->revision != 0x5)
> + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> goto out;
>
> /* VSC SDP Payload for DB16 through DB18 */
> @@ -5275,6 +5301,7 @@ intel_dp_detect(struct drm_connector
> *connector,
> if (status == connector_status_disconnected) {
> memset(&intel_dp->compliance, 0, sizeof(intel_dp-
> >compliance));
> memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp-
> >dsc_dpcd));
> + intel_dp->psr.sink_panel_replay_support = false;
>
> if (intel_dp->is_mst) {
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2d1c42a5e684..65f68997281e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -43,6 +43,7 @@
> #include "intel_dpio_phy.h"
> #include "intel_hdcp.h"
> #include "intel_hotplug.h"
> +#include "intel_psr.h"
> #include "skl_scaler.h"
>
> static int intel_dp_mst_check_constraints(struct drm_i915_private
> *i915, int bpp,
> @@ -383,6 +384,8 @@ static int intel_dp_mst_compute_config(struct
> intel_encoder *encoder,
>
> intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>
> + intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 24eed99e8811..f2209fc94125 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -171,6 +171,15 @@
> * irrelevant for normal operation.
> */
>
> +bool intel_encoder_can_psr(struct intel_encoder *encoder)
> +{
> + if (intel_encoder_is_dp(encoder) || encoder->type ==
> INTEL_OUTPUT_DP_MST)
> + return CAN_PSR(enc_to_intel_dp(encoder)) ||
> + CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
> + else
> + return false;
> +}
> +
> static bool psr_global_enabled(struct intel_dp *intel_dp)
> {
> struct intel_connector *connector = intel_dp-
> >attached_connector;
> @@ -473,6 +482,24 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
> intel_dp->psr.su_y_granularity = y;
> }
>
> +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u8 pr_dpcd = 0;
> +
> + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> &pr_dpcd);
> +
> + if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Panel replay is not supported by
> panel\n");
> + return;
> + }
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "Panel replay is supported by panel\n");
> + intel_dp->psr.sink_panel_replay_support = true;
> +}
> +
> static void _psr_init_dpcd(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *i915 =
> @@ -522,12 +549,13 @@ static void _psr_init_dpcd(struct intel_dp
> *intel_dp)
>
> void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> {
> + _panel_replay_init_dpcd(intel_dp);
> +
> drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> >psr_dpcd,
> sizeof(intel_dp->psr_dpcd));
>
> if (intel_dp->psr_dpcd[0])
> _psr_init_dpcd(intel_dp);
> - /* TODO: Add PR case here */
>
> if (intel_dp->psr.sink_psr2_support) {
> intel_dp->psr.colorimetry_support =
> @@ -1208,13 +1236,11 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> -void intel_psr_compute_config(struct intel_dp *intel_dp,
> - struct intel_crtc_state *crtc_state,
> - struct drm_connector_state *conn_state)
> +static bool _psr_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> + const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> int psr_setup_time;
>
> /*
> @@ -1222,10 +1248,36 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> * So if VRR is enabled, do not enable PSR.
> */
> if (crtc_state->vrr.enable)
> - return;
> + return false;
>
> if (!CAN_PSR(intel_dp))
> - return;
> + return false;
> +
> + psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> + if (psr_setup_time < 0) {
> + drm_dbg_kms(&dev_priv->drm,
> + "PSR condition failed: Invalid PSR setup
> time (0x%02x)\n",
> + intel_dp->psr_dpcd[1]);
> + return false;
> + }
> +
> + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay
> - 1) {
> + drm_dbg_kms(&dev_priv->drm,
> + "PSR condition failed: PSR setup time (%d
> us) too long\n",
> + psr_setup_time);
> + return false;
> + }
> +
> + return true;
> +}
> +
> +void intel_psr_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
>
> if (!psr_global_enabled(intel_dp)) {
> drm_dbg_kms(&dev_priv->drm, "PSR disabled by
> flag\n");
> @@ -1235,7 +1287,6 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> if (intel_dp->psr.sink_not_reliable) {
> drm_dbg_kms(&dev_priv->drm,
> "PSR sink implementation is not
> reliable\n");
> - return;
You should not remove this return here?
BR,
Jouni Högander
> }
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -1244,23 +1295,11 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> return;
> }
>
> - psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> - if (psr_setup_time < 0) {
> - drm_dbg_kms(&dev_priv->drm,
> - "PSR condition failed: Invalid PSR setup
> time (0x%02x)\n",
> - intel_dp->psr_dpcd[1]);
> - return;
> - }
> -
> - if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> - adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay
> - 1) {
> - drm_dbg_kms(&dev_priv->drm,
> - "PSR condition failed: PSR setup time (%d
> us) too long\n",
> - psr_setup_time);
> - return;
> - }
> + if (CAN_PANEL_REPLAY(intel_dp))
> + crtc_state->has_panel_replay = true;
> + else
> + crtc_state->has_psr = _psr_compute_config(intel_dp,
> crtc_state);
>
> - crtc_state->has_psr = true;
> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> crtc_state);
>
> crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> @@ -2705,7 +2744,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port =
> dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - if (!HAS_PSR(dev_priv))
> + if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
> return;
>
> /*
> @@ -2723,7 +2762,10 @@ void intel_psr_init(struct intel_dp *intel_dp)
> return;
> }
>
> - intel_dp->psr.source_support = true;
> + if (HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp))
> + intel_dp->psr.source_panel_replay_support = true;
> + else
> + intel_dp->psr.source_support = true;
>
> /* Set link_standby x link_off defaults */
> if (DISPLAY_VER(dev_priv) < 12)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 0b95e8aa615f..1179abc354df 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -21,6 +21,13 @@ struct intel_encoder;
> struct intel_plane;
> struct intel_plane_state;
>
> +#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> + (intel_dp)->psr.source_support)
> +
> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> + (intel_dp)-
> >psr.source_panel_replay_support)
> +
> +bool intel_encoder_can_psr(struct intel_encoder *encoder);
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH v5 4/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
2023-09-05 7:35 ` Animesh Manna
@ 2023-09-05 7:35 ` Animesh Manna
-1 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
Due to similarity panel replay dpcd initialization got added in psr
function which is specific for edp panel. This patch enables panel
replay initialization for dp connector.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f2209fc94125..4e9c126a47ff 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2747,6 +2747,9 @@ void intel_psr_init(struct intel_dp *intel_dp)
if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
return;
+ if (!intel_dp_is_edp(intel_dp))
+ intel_psr_init_dpcd(intel_dp);
+
/*
* HSW spec explicitly says PSR is tied to port A.
* BDW+ platforms have a instance of PSR registers per transcoder but
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v5 4/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
@ 2023-09-05 7:35 ` Animesh Manna
0 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, jouni.hogander, Animesh Manna, arun.r.murthy
Due to similarity panel replay dpcd initialization got added in psr
function which is specific for edp panel. This patch enables panel
replay initialization for dp connector.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f2209fc94125..4e9c126a47ff 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2747,6 +2747,9 @@ void intel_psr_init(struct intel_dp *intel_dp)
if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
return;
+ if (!intel_dp_is_edp(intel_dp))
+ intel_psr_init_dpcd(intel_dp);
+
/*
* HSW spec explicitly says PSR is tied to port A.
* BDW+ platforms have a instance of PSR registers per transcoder but
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH v5 5/6] drm/i915/panelreplay: enable/disable panel replay
2023-09-05 7:35 ` Animesh Manna
@ 2023-09-05 7:35 ` Animesh Manna
-1 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Bspec: 1407940617
v1: Initial version.
v2:
- Use pr_* flags instead psr_* flags. [Jouni]
- Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni]
v3: Cover letter updated and selective fetch condition check is added
before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]
v4: Selective fetch related PSR2_MAN_TRK_CTL programmming dropped. [Jouni]
Note: Initial plan is to enable panel replay in full-screen live active
frame update mode. In a incremental approach panel replay will be enabled
in selctive update mode if there is any gap in curent implementation.
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 65 ++++++++++++++-----
2 files changed, 50 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4022d6d8281a..b1383988b656 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1696,6 +1696,7 @@ struct intel_psr {
u16 su_y_granularity;
bool source_panel_replay_support;
bool sink_panel_replay_support;
+ bool panel_replay_enabled;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4e9c126a47ff..5cbf08a4c94c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -606,8 +606,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
- /* Enable ALPM at sink for psr2 */
+ if (intel_dp->psr.panel_replay_enabled) {
+ drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+ DP_PANEL_REPLAY_ENABLE);
+ return;
+ }
+
if (intel_dp->psr.psr2_enabled) {
+ /* Enable ALPM at sink for psr2 */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE |
DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -757,6 +763,14 @@ static int psr2_block_count(struct intel_dp *intel_dp)
return psr2_block_count_lines(intel_dp) / 4;
}
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+ TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1320,18 +1334,23 @@ void intel_psr_get_config(struct intel_encoder *encoder,
return;
intel_dp = &dig_port->dp;
- if (!CAN_PSR(intel_dp))
+ if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
return;
mutex_lock(&intel_dp->psr.lock);
if (!intel_dp->psr.enabled)
goto unlock;
- /*
- * Not possible to read EDP_PSR/PSR2_CTL registers as it is
- * enabled/disabled because of frontbuffer tracking and others.
- */
- pipe_config->has_psr = true;
+ if (intel_dp->psr.panel_replay_enabled) {
+ pipe_config->has_panel_replay = true;
+ } else {
+ /*
+ * Not possible to read EDP_PSR/PSR2_CTL registers as it is
+ * enabled/disabled because of frontbuffer tracking and others.
+ */
+ pipe_config->has_psr = true;
+ }
+
pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
@@ -1368,8 +1387,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
lockdep_assert_held(&intel_dp->psr.lock);
- /* psr1 and psr2 are mutually exclusive.*/
- if (intel_dp->psr.psr2_enabled)
+ /* psr1, psr2 and panel-replay are mutually exclusive.*/
+ if (intel_dp->psr.panel_replay_enabled)
+ dg2_activate_panel_replay(intel_dp);
+ else if (intel_dp->psr.psr2_enabled)
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);
@@ -1547,6 +1568,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+ intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
intel_dp->psr.busy_frontbuffer_bits = 0;
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
@@ -1562,8 +1584,12 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
if (!psr_interrupt_error_check(intel_dp))
return;
- drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
- intel_dp->psr.psr2_enabled ? "2" : "1");
+ if (intel_dp->psr.panel_replay_enabled)
+ drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n");
+ else
+ drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
+ intel_dp->psr.psr2_enabled ? "2" : "1");
+
intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
intel_psr_enable_sink(intel_dp);
@@ -1592,7 +1618,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
return;
}
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.panel_replay_enabled) {
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
+ TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
+ } else if (intel_dp->psr.psr2_enabled) {
tgl_disallow_dc3co_on_psr2_exit(intel_dp);
val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
@@ -1641,8 +1670,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
if (!intel_dp->psr.enabled)
return;
- drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
- intel_dp->psr.psr2_enabled ? "2" : "1");
+ if (intel_dp->psr.panel_replay_enabled)
+ drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n");
+ else
+ drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
+ intel_dp->psr.psr2_enabled ? "2" : "1");
intel_psr_exit(intel_dp);
intel_psr_wait_exit_locked(intel_dp);
@@ -1675,6 +1707,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
intel_dp->psr.enabled = false;
+ intel_dp->psr.panel_replay_enabled = false;
intel_dp->psr.psr2_enabled = false;
intel_dp->psr.psr2_sel_fetch_enabled = false;
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
@@ -2244,7 +2277,7 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_encoder *encoder;
- if (!crtc_state->has_psr)
+ if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
return;
for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
@@ -2291,7 +2324,7 @@ void intel_psr_post_plane_update(const struct intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!HAS_PSR(dev_priv))
+ if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
return;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v5 5/6] drm/i915/panelreplay: enable/disable panel replay
@ 2023-09-05 7:35 ` Animesh Manna
0 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, jouni.hogander, Animesh Manna, arun.r.murthy
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Bspec: 1407940617
v1: Initial version.
v2:
- Use pr_* flags instead psr_* flags. [Jouni]
- Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni]
v3: Cover letter updated and selective fetch condition check is added
before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]
v4: Selective fetch related PSR2_MAN_TRK_CTL programmming dropped. [Jouni]
Note: Initial plan is to enable panel replay in full-screen live active
frame update mode. In a incremental approach panel replay will be enabled
in selctive update mode if there is any gap in curent implementation.
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 65 ++++++++++++++-----
2 files changed, 50 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4022d6d8281a..b1383988b656 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1696,6 +1696,7 @@ struct intel_psr {
u16 su_y_granularity;
bool source_panel_replay_support;
bool sink_panel_replay_support;
+ bool panel_replay_enabled;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4e9c126a47ff..5cbf08a4c94c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -606,8 +606,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
- /* Enable ALPM at sink for psr2 */
+ if (intel_dp->psr.panel_replay_enabled) {
+ drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+ DP_PANEL_REPLAY_ENABLE);
+ return;
+ }
+
if (intel_dp->psr.psr2_enabled) {
+ /* Enable ALPM at sink for psr2 */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE |
DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -757,6 +763,14 @@ static int psr2_block_count(struct intel_dp *intel_dp)
return psr2_block_count_lines(intel_dp) / 4;
}
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+ TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1320,18 +1334,23 @@ void intel_psr_get_config(struct intel_encoder *encoder,
return;
intel_dp = &dig_port->dp;
- if (!CAN_PSR(intel_dp))
+ if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
return;
mutex_lock(&intel_dp->psr.lock);
if (!intel_dp->psr.enabled)
goto unlock;
- /*
- * Not possible to read EDP_PSR/PSR2_CTL registers as it is
- * enabled/disabled because of frontbuffer tracking and others.
- */
- pipe_config->has_psr = true;
+ if (intel_dp->psr.panel_replay_enabled) {
+ pipe_config->has_panel_replay = true;
+ } else {
+ /*
+ * Not possible to read EDP_PSR/PSR2_CTL registers as it is
+ * enabled/disabled because of frontbuffer tracking and others.
+ */
+ pipe_config->has_psr = true;
+ }
+
pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
@@ -1368,8 +1387,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
lockdep_assert_held(&intel_dp->psr.lock);
- /* psr1 and psr2 are mutually exclusive.*/
- if (intel_dp->psr.psr2_enabled)
+ /* psr1, psr2 and panel-replay are mutually exclusive.*/
+ if (intel_dp->psr.panel_replay_enabled)
+ dg2_activate_panel_replay(intel_dp);
+ else if (intel_dp->psr.psr2_enabled)
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);
@@ -1547,6 +1568,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+ intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
intel_dp->psr.busy_frontbuffer_bits = 0;
intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
@@ -1562,8 +1584,12 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
if (!psr_interrupt_error_check(intel_dp))
return;
- drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
- intel_dp->psr.psr2_enabled ? "2" : "1");
+ if (intel_dp->psr.panel_replay_enabled)
+ drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n");
+ else
+ drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
+ intel_dp->psr.psr2_enabled ? "2" : "1");
+
intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
intel_psr_enable_sink(intel_dp);
@@ -1592,7 +1618,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
return;
}
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.panel_replay_enabled) {
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
+ TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
+ } else if (intel_dp->psr.psr2_enabled) {
tgl_disallow_dc3co_on_psr2_exit(intel_dp);
val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
@@ -1641,8 +1670,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
if (!intel_dp->psr.enabled)
return;
- drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
- intel_dp->psr.psr2_enabled ? "2" : "1");
+ if (intel_dp->psr.panel_replay_enabled)
+ drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n");
+ else
+ drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
+ intel_dp->psr.psr2_enabled ? "2" : "1");
intel_psr_exit(intel_dp);
intel_psr_wait_exit_locked(intel_dp);
@@ -1675,6 +1707,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
intel_dp->psr.enabled = false;
+ intel_dp->psr.panel_replay_enabled = false;
intel_dp->psr.psr2_enabled = false;
intel_dp->psr.psr2_sel_fetch_enabled = false;
intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
@@ -2244,7 +2277,7 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_encoder *encoder;
- if (!crtc_state->has_psr)
+ if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
return;
for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
@@ -2291,7 +2324,7 @@ void intel_psr_post_plane_update(const struct intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!HAS_PSR(dev_priv))
+ if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
return;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH v5 6/6] drm/i915/panelreplay: Debugfs support for panel replay
2023-09-05 7:35 ` Animesh Manna
@ 2023-09-05 7:35 ` Animesh Manna
-1 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: jani.nikula
Add debugfs support which will print source and sink status
per connector basis.
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 70 ++++++++++++++++--------
1 file changed, 48 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5cbf08a4c94c..f50f110feb09 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3044,7 +3044,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
status = live_status[status_val];
}
- seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
+ seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val);
}
static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
@@ -3057,18 +3057,23 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
bool enabled;
u32 val;
- seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support));
- if (psr->sink_support)
+ seq_printf(m, "Sink support: PSR = %s, Panel Replay = %s",
+ str_yes_no(psr->sink_support),
+ str_yes_no(psr->sink_panel_replay_support));
+
+ if (psr->sink_support || psr->sink_panel_replay_support)
seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
seq_puts(m, "\n");
- if (!psr->sink_support)
+ if (!(psr->sink_support || psr->sink_panel_replay_support))
return 0;
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
mutex_lock(&psr->lock);
- if (psr->enabled)
+ if (psr->panel_replay_enabled)
+ status = "Panel Replay Enabled";
+ else if (psr->enabled)
status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
else
status = "disabled";
@@ -3081,14 +3086,17 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
goto unlock;
}
- if (psr->psr2_enabled) {
+ if (psr->panel_replay_enabled) {
+ val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder));
+ enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
+ } else if (psr->psr2_enabled) {
val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
enabled = val & EDP_PSR2_ENABLE;
} else {
val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder));
enabled = val & EDP_PSR_ENABLE;
}
- seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
+ seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n",
str_enabled_disabled(enabled), val);
psr_source_status(intel_dp, m);
seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
@@ -3230,6 +3238,7 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
{
struct intel_connector *connector = m->private;
struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct intel_psr *psr = &intel_dp->psr;
static const char * const sink_status[] = {
"inactive",
"transition to active, capture and display",
@@ -3240,27 +3249,47 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
"reserved",
"sink internal error",
};
+ static const char * const panel_replay_status[] = {
+ "Sink device frame is locked to the Source device",
+ "Sink device is coasting, using the VTotal target",
+ "Sink device is governing the frame rate (frame rate unlock is granted)",
+ "Sink device in the process of re-locking with the Source device",
+ };
const char *str;
int ret;
- u8 val;
+ u8 val, temp;
- if (!CAN_PSR(intel_dp)) {
- seq_puts(m, "PSR Unsupported\n");
+ if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) {
+ seq_puts(m, "PSR/Panel-Replay Unsupported\n");
return -ENODEV;
}
if (connector->base.status != connector_status_connected)
return -ENODEV;
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
- if (ret != 1)
- return ret < 0 ? ret : -EIO;
+ if (psr->panel_replay_enabled) {
+ ret = drm_dp_dpcd_readb(&intel_dp->aux,
+ DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS, &val);
+ if (ret != 1)
+ return ret < 0 ? ret : -EIO;
- val &= DP_PSR_SINK_STATE_MASK;
- if (val < ARRAY_SIZE(sink_status))
- str = sink_status[val];
- else
- str = "unknown";
+ temp = val & DP_SINK_FRAME_LOCKED_MASK;
+ temp >>= DP_SINK_FRAME_LOCKED_SHIFT;
+ if (temp < ARRAY_SIZE(panel_replay_status))
+ str = panel_replay_status[temp];
+ else
+ str = "unknown";
+ } else {
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
+ if (ret != 1)
+ return ret < 0 ? ret : -EIO;
+
+ val &= DP_PSR_SINK_STATE_MASK;
+ if (val < ARRAY_SIZE(sink_status))
+ str = sink_status[val];
+ else
+ str = "unknown";
+ }
seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
@@ -3282,13 +3311,10 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector)
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct dentry *root = connector->base.debugfs_entry;
- if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
- return;
-
debugfs_create_file("i915_psr_sink_status", 0444, root,
connector, &i915_psr_sink_status_fops);
- if (HAS_PSR(i915))
+ if (HAS_PSR(i915) || HAS_DP20(i915))
debugfs_create_file("i915_psr_status", 0444, root,
connector, &i915_psr_status_fops);
}
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v5 6/6] drm/i915/panelreplay: Debugfs support for panel replay
@ 2023-09-05 7:35 ` Animesh Manna
0 siblings, 0 replies; 27+ messages in thread
From: Animesh Manna @ 2023-09-05 7:35 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: jani.nikula, jouni.hogander, Animesh Manna, arun.r.murthy
Add debugfs support which will print source and sink status
per connector basis.
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 70 ++++++++++++++++--------
1 file changed, 48 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5cbf08a4c94c..f50f110feb09 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -3044,7 +3044,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m)
status = live_status[status_val];
}
- seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val);
+ seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val);
}
static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
@@ -3057,18 +3057,23 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
bool enabled;
u32 val;
- seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support));
- if (psr->sink_support)
+ seq_printf(m, "Sink support: PSR = %s, Panel Replay = %s",
+ str_yes_no(psr->sink_support),
+ str_yes_no(psr->sink_panel_replay_support));
+
+ if (psr->sink_support || psr->sink_panel_replay_support)
seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
seq_puts(m, "\n");
- if (!psr->sink_support)
+ if (!(psr->sink_support || psr->sink_panel_replay_support))
return 0;
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
mutex_lock(&psr->lock);
- if (psr->enabled)
+ if (psr->panel_replay_enabled)
+ status = "Panel Replay Enabled";
+ else if (psr->enabled)
status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";
else
status = "disabled";
@@ -3081,14 +3086,17 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
goto unlock;
}
- if (psr->psr2_enabled) {
+ if (psr->panel_replay_enabled) {
+ val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder));
+ enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
+ } else if (psr->psr2_enabled) {
val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder));
enabled = val & EDP_PSR2_ENABLE;
} else {
val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder));
enabled = val & EDP_PSR_ENABLE;
}
- seq_printf(m, "Source PSR ctl: %s [0x%08x]\n",
+ seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n",
str_enabled_disabled(enabled), val);
psr_source_status(intel_dp, m);
seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
@@ -3230,6 +3238,7 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
{
struct intel_connector *connector = m->private;
struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct intel_psr *psr = &intel_dp->psr;
static const char * const sink_status[] = {
"inactive",
"transition to active, capture and display",
@@ -3240,27 +3249,47 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data)
"reserved",
"sink internal error",
};
+ static const char * const panel_replay_status[] = {
+ "Sink device frame is locked to the Source device",
+ "Sink device is coasting, using the VTotal target",
+ "Sink device is governing the frame rate (frame rate unlock is granted)",
+ "Sink device in the process of re-locking with the Source device",
+ };
const char *str;
int ret;
- u8 val;
+ u8 val, temp;
- if (!CAN_PSR(intel_dp)) {
- seq_puts(m, "PSR Unsupported\n");
+ if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) {
+ seq_puts(m, "PSR/Panel-Replay Unsupported\n");
return -ENODEV;
}
if (connector->base.status != connector_status_connected)
return -ENODEV;
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
- if (ret != 1)
- return ret < 0 ? ret : -EIO;
+ if (psr->panel_replay_enabled) {
+ ret = drm_dp_dpcd_readb(&intel_dp->aux,
+ DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS, &val);
+ if (ret != 1)
+ return ret < 0 ? ret : -EIO;
- val &= DP_PSR_SINK_STATE_MASK;
- if (val < ARRAY_SIZE(sink_status))
- str = sink_status[val];
- else
- str = "unknown";
+ temp = val & DP_SINK_FRAME_LOCKED_MASK;
+ temp >>= DP_SINK_FRAME_LOCKED_SHIFT;
+ if (temp < ARRAY_SIZE(panel_replay_status))
+ str = panel_replay_status[temp];
+ else
+ str = "unknown";
+ } else {
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);
+ if (ret != 1)
+ return ret < 0 ? ret : -EIO;
+
+ val &= DP_PSR_SINK_STATE_MASK;
+ if (val < ARRAY_SIZE(sink_status))
+ str = sink_status[val];
+ else
+ str = "unknown";
+ }
seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);
@@ -3282,13 +3311,10 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector)
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct dentry *root = connector->base.debugfs_entry;
- if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
- return;
-
debugfs_create_file("i915_psr_sink_status", 0444, root,
connector, &i915_psr_sink_status_fops);
- if (HAS_PSR(i915))
+ if (HAS_PSR(i915) || HAS_DP20(i915))
debugfs_create_file("i915_psr_status", 0444, root,
connector, &i915_psr_status_fops);
}
--
2.29.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Panel replay phase1 implementation (rev7)
2023-09-05 7:35 ` Animesh Manna
` (6 preceding siblings ...)
(?)
@ 2023-09-05 21:06 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-09-05 21:06 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
== Series Details ==
Series: Panel replay phase1 implementation (rev7)
URL : https://patchwork.freedesktop.org/series/94470/
State : warning
== Summary ==
Error: dim checkpatch failed
df46f8fc2937 drm/panelreplay: dpcd register definition for panelreplay
a4cfe5eb05ad drm/i915/psr: Move psr specific dpcd init into own function
-:55: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED'
#55: FILE: drivers/gpu/drm/i915/display/intel_psr.c:500:
+ if (DISPLAY_VER(i915) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
total: 0 errors, 0 warnings, 1 checks, 70 lines checked
c3af614a25dd drm/i915/panelreplay: Initializaton and compute config for panel replay
-:362: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects?
#362: FILE: drivers/gpu/drm/i915/display/intel_psr.h:24:
+#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
+ (intel_dp)->psr.source_support)
-:365: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible side-effects?
#365: FILE: drivers/gpu/drm/i915/display/intel_psr.h:27:
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
+ (intel_dp)->psr.source_panel_replay_support)
total: 0 errors, 0 warnings, 2 checks, 290 lines checked
a5ed631e2878 drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
2d8dc819debf drm/i915/panelreplay: enable/disable panel replay
a12bb3cdd5f6 drm/i915/panelreplay: Debugfs support for panel replay
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev7)
2023-09-05 7:35 ` Animesh Manna
` (7 preceding siblings ...)
(?)
@ 2023-09-05 21:06 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-09-05 21:06 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
== Series Details ==
Series: Panel replay phase1 implementation (rev7)
URL : https://patchwork.freedesktop.org/series/94470/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for Panel replay phase1 implementation (rev7)
2023-09-05 7:35 ` Animesh Manna
` (8 preceding siblings ...)
(?)
@ 2023-09-05 21:25 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-09-05 21:25 UTC (permalink / raw)
To: Manna, Animesh; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10726 bytes --]
== Series Details ==
Series: Panel replay phase1 implementation (rev7)
URL : https://patchwork.freedesktop.org/series/94470/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13599 -> Patchwork_94470v7
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_94470v7 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_94470v7, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/index.html
Participating hosts (38 -> 37)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_94470v7:
### IGT changes ###
#### Possible regressions ####
* igt@debugfs_test@read_all_entries:
- fi-hsw-4770: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/fi-hsw-4770/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/fi-hsw-4770/igt@debugfs_test@read_all_entries.html
- fi-ivb-3770: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/fi-ivb-3770/igt@debugfs_test@read_all_entries.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/fi-ivb-3770/igt@debugfs_test@read_all_entries.html
- fi-elk-e7500: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/fi-elk-e7500/igt@debugfs_test@read_all_entries.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/fi-elk-e7500/igt@debugfs_test@read_all_entries.html
- fi-ilk-650: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/fi-ilk-650/igt@debugfs_test@read_all_entries.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/fi-ilk-650/igt@debugfs_test@read_all_entries.html
- fi-blb-e6850: [PASS][9] -> [ABORT][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/fi-blb-e6850/igt@debugfs_test@read_all_entries.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/fi-blb-e6850/igt@debugfs_test@read_all_entries.html
* igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
Known issues
------------
Here are the changes found in Patchwork_94470v7 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-adlp-6: NOTRUN -> [ABORT][13] ([i915#8668])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adlp-6/igt@i915_pm_backlight@basic-brightness@edp-1.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- bat-adln-1: NOTRUN -> [ABORT][14] ([i915#7977] / [i915#8469] / [i915#8668])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adln-1/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3: [PASS][15] -> [FAIL][16] ([fdo#103375])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_psr@cursor_plane_move:
- bat-adln-1: [PASS][17] -> [SKIP][18] ([i915#1072]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-adln-1/igt@kms_psr@cursor_plane_move.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adln-1/igt@kms_psr@cursor_plane_move.html
- fi-skl-6600u: [PASS][19] -> [SKIP][20] ([fdo#109271]) +3 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/fi-skl-6600u/igt@kms_psr@cursor_plane_move.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/fi-skl-6600u/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_mmap_gtt:
- bat-adln-1: NOTRUN -> [SKIP][21] ([i915#1072])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adln-1/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@sprite_plane_onoff:
- bat-mtlp-8: [PASS][22] -> [SKIP][23] ([i915#1072]) +2 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-mtlp-8/igt@kms_psr@sprite_plane_onoff.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-mtlp-8/igt@kms_psr@sprite_plane_onoff.html
- bat-jsl-1: [PASS][24] -> [SKIP][25] ([i915#1072]) +3 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-jsl-1/igt@kms_psr@sprite_plane_onoff.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-jsl-1/igt@kms_psr@sprite_plane_onoff.html
- bat-adlp-6: NOTRUN -> [SKIP][26] ([i915#1072]) +2 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adlp-6/igt@kms_psr@sprite_plane_onoff.html
- bat-jsl-3: [PASS][27] -> [SKIP][28] ([i915#1072]) +3 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-jsl-3/igt@kms_psr@sprite_plane_onoff.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-jsl-3/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adlp-6: NOTRUN -> [SKIP][29] ([i915#3555])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adlp-6/igt@kms_setmode@basic-clone-single-crtc.html
- bat-adln-1: NOTRUN -> [SKIP][30] ([i915#3555])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adln-1/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@kms_chamelium_frames@dp-crc-fast:
- {bat-dg2-13}: [DMESG-WARN][31] ([Intel XE#485]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-dg2-13/igt@kms_chamelium_frames@dp-crc-fast.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-dg2-13/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_flip@basic-flip-vs-wf_vblank@a-dp6:
- bat-adlp-11: [FAIL][33] ([i915#6121]) -> [PASS][34] +4 other tests pass
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp6.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vblank@a-dp6.html
* igt@kms_flip@basic-flip-vs-wf_vblank@c-dp5:
- bat-adlp-11: [DMESG-WARN][35] ([i915#6868]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp5.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adlp-11/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp5.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][37] ([IGT#3] / [i915#6121]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
#### Warnings ####
* igt@kms_psr@primary_mmap_gtt:
- bat-mtlp-8: [SKIP][39] ([i915#4077]) -> [SKIP][40] ([i915#1072])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-mtlp-8/igt@kms_psr@primary_mmap_gtt.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-mtlp-8/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@primary_page_flip:
- bat-adlp-6: [ABORT][41] ([i915#8442] / [i915#8668]) -> [SKIP][42] ([i915#1072])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-adlp-6/igt@kms_psr@primary_page_flip.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adlp-6/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@sprite_plane_onoff:
- bat-adln-1: [ABORT][43] ([i915#8442] / [i915#8668]) -> [SKIP][44] ([i915#1072])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13599/bat-adln-1/igt@kms_psr@sprite_plane_onoff.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/bat-adln-1/igt@kms_psr@sprite_plane_onoff.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868
[i915#7977]: https://gitlab.freedesktop.org/drm/intel/issues/7977
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8469]: https://gitlab.freedesktop.org/drm/intel/issues/8469
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
Build changes
-------------
* Linux: CI_DRM_13599 -> Patchwork_94470v7
CI-20190529: 20190529
CI_DRM_13599: 58fe10f34e80d0eeb5609128faa135260623a715 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7468: 7468
Patchwork_94470v7: 58fe10f34e80d0eeb5609128faa135260623a715 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4c1f8dd6b84d drm/i915/panelreplay: Debugfs support for panel replay
d406cf69f7b5 drm/i915/panelreplay: enable/disable panel replay
7a8965e09e77 drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
5003c7b88217 drm/i915/panelreplay: Initializaton and compute config for panel replay
22a975685f05 drm/i915/psr: Move psr specific dpcd init into own function
7755b8dd1523 drm/panelreplay: dpcd register definition for panelreplay
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v7/index.html
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