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From: Jisheng Zhang <jszhang@kernel.org>
To: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Drew Fustini <dfustini@baylibre.com>
Subject: [PATCH v2] riscv: dts: thead: set dma-noncoherent to soc bus
Date: Tue, 12 Sep 2023 15:22:32 +0800	[thread overview]
Message-ID: <20230912072232.2455-1-jszhang@kernel.org> (raw)

riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
dma coherent, so set dma-noncoherent to reflect this fact.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Tested-by: Drew Fustini <dfustini@baylibre.com>
---

Since v1:
 - rebase on v6.6-rc1
 - collect Tested-by tag

 arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index ce708183b6f6..ff364709a6df 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -139,6 +139,7 @@ soc {
 		interrupt-parent = <&plic>;
 		#address-cells = <2>;
 		#size-cells = <2>;
+		dma-noncoherent;
 		ranges;
 
 		plic: interrupt-controller@ffd8000000 {
-- 
2.40.1


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WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
	Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Drew Fustini <dfustini@baylibre.com>
Subject: [PATCH v2] riscv: dts: thead: set dma-noncoherent to soc bus
Date: Tue, 12 Sep 2023 15:22:32 +0800	[thread overview]
Message-ID: <20230912072232.2455-1-jszhang@kernel.org> (raw)

riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
dma coherent, so set dma-noncoherent to reflect this fact.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Tested-by: Drew Fustini <dfustini@baylibre.com>
---

Since v1:
 - rebase on v6.6-rc1
 - collect Tested-by tag

 arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index ce708183b6f6..ff364709a6df 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -139,6 +139,7 @@ soc {
 		interrupt-parent = <&plic>;
 		#address-cells = <2>;
 		#size-cells = <2>;
+		dma-noncoherent;
 		ranges;
 
 		plic: interrupt-controller@ffd8000000 {
-- 
2.40.1


             reply	other threads:[~2023-09-12  7:34 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-12  7:22 Jisheng Zhang [this message]
2023-09-12  7:22 ` [PATCH v2] riscv: dts: thead: set dma-noncoherent to soc bus Jisheng Zhang
2023-09-12 14:48 ` Guo Ren
2023-09-12 14:48   ` Guo Ren
2023-09-12 16:27 ` Conor Dooley
2023-09-12 16:27   ` Conor Dooley
2023-09-13 15:15   ` Jisheng Zhang
2023-09-13 15:15     ` Jisheng Zhang
2023-09-13 15:44     ` Conor Dooley
2023-09-13 15:44       ` Conor Dooley
2023-09-20  8:36       ` Conor Dooley
2023-09-20  8:36         ` Conor Dooley
2023-09-21  9:24         ` Jisheng Zhang
2023-09-21  9:24           ` Jisheng Zhang
2023-09-21 10:08           ` Conor Dooley
2023-09-21 10:08             ` Conor Dooley
2023-10-16 17:10             ` Drew Fustini
2023-10-16 17:10               ` Drew Fustini
2023-10-17 16:09               ` Jisheng Zhang
2023-10-17 16:09                 ` Jisheng Zhang
2023-10-17 20:33                 ` Arnd Bergmann
2023-10-17 20:33                   ` Arnd Bergmann
2023-11-12  0:55 ` patchwork-bot+linux-riscv
2023-11-12  0:55   ` patchwork-bot+linux-riscv

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