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From: Simon Horman <horms@kernel.org>
To: Pu Lehui <pulehui@huaweicloud.com>
Cc: bpf@vger.kernel.org, linux-riscv@lists.infradead.org,
	netdev@vger.kernel.org, "Björn Töpel" <bjorn@kernel.org>,
	"Alexei Starovoitov" <ast@kernel.org>,
	"Daniel Borkmann" <daniel@iogearbox.net>,
	"Andrii Nakryiko" <andrii@kernel.org>,
	"Martin KaFai Lau" <martin.lau@linux.dev>,
	"Song Liu" <song@kernel.org>, "Yonghong Song" <yhs@fb.com>,
	"John Fastabend" <john.fastabend@gmail.com>,
	"KP Singh" <kpsingh@kernel.org>,
	"Stanislav Fomichev" <sdf@google.com>,
	"Hao Luo" <haoluo@google.com>, "Jiri Olsa" <jolsa@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Luke Nelson" <luke.r.nels@gmail.com>,
	"Pu Lehui" <pulehui@huawei.com>
Subject: Re: [PATCH bpf-next 3/6] riscv, bpf: Simplify sext and zext logics in branch instructions
Date: Sat, 16 Sep 2023 16:47:42 +0200	[thread overview]
Message-ID: <20230916144742.GB1125562@kernel.org> (raw)
In-Reply-To: <20230913153413.1446068-4-pulehui@huaweicloud.com>

On Wed, Sep 13, 2023 at 11:34:10PM +0800, Pu Lehui wrote:
> From: Pu Lehui <pulehui@huawei.com>
> 
> There are many extension helpers in the current branch instructions, and
> the implementation is a bit complicated. We simplify this logic through
> two simple extension helpers with alternate register.
> 
> Signed-off-by: Pu Lehui <pulehui@huawei.com>
> ---
>  arch/riscv/net/bpf_jit_comp64.c | 82 +++++++++++++--------------------
>  1 file changed, 31 insertions(+), 51 deletions(-)
> 
> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> index 4a649e195..1728ce16d 100644
> --- a/arch/riscv/net/bpf_jit_comp64.c
> +++ b/arch/riscv/net/bpf_jit_comp64.c
> @@ -141,6 +141,19 @@ static bool in_auipc_jalr_range(s64 val)
>  		val < ((1L << 31) - (1L << 11));
>  }
>  
> +/* Modify rd pointer to alternate reg to avoid corrupting orignal reg */

Hi Pu Lehui,

nit: original

I suggest running checkpatch --codespell over this series before submitting
v2.

WARNING: multiple messages have this Message-ID (diff)
From: Simon Horman <horms@kernel.org>
To: Pu Lehui <pulehui@huaweicloud.com>
Cc: bpf@vger.kernel.org, linux-riscv@lists.infradead.org,
	netdev@vger.kernel.org, "Björn Töpel" <bjorn@kernel.org>,
	"Alexei Starovoitov" <ast@kernel.org>,
	"Daniel Borkmann" <daniel@iogearbox.net>,
	"Andrii Nakryiko" <andrii@kernel.org>,
	"Martin KaFai Lau" <martin.lau@linux.dev>,
	"Song Liu" <song@kernel.org>, "Yonghong Song" <yhs@fb.com>,
	"John Fastabend" <john.fastabend@gmail.com>,
	"KP Singh" <kpsingh@kernel.org>,
	"Stanislav Fomichev" <sdf@google.com>,
	"Hao Luo" <haoluo@google.com>, "Jiri Olsa" <jolsa@kernel.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Luke Nelson" <luke.r.nels@gmail.com>,
	"Pu Lehui" <pulehui@huawei.com>
Subject: Re: [PATCH bpf-next 3/6] riscv, bpf: Simplify sext and zext logics in branch instructions
Date: Sat, 16 Sep 2023 16:47:42 +0200	[thread overview]
Message-ID: <20230916144742.GB1125562@kernel.org> (raw)
In-Reply-To: <20230913153413.1446068-4-pulehui@huaweicloud.com>

On Wed, Sep 13, 2023 at 11:34:10PM +0800, Pu Lehui wrote:
> From: Pu Lehui <pulehui@huawei.com>
> 
> There are many extension helpers in the current branch instructions, and
> the implementation is a bit complicated. We simplify this logic through
> two simple extension helpers with alternate register.
> 
> Signed-off-by: Pu Lehui <pulehui@huawei.com>
> ---
>  arch/riscv/net/bpf_jit_comp64.c | 82 +++++++++++++--------------------
>  1 file changed, 31 insertions(+), 51 deletions(-)
> 
> diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
> index 4a649e195..1728ce16d 100644
> --- a/arch/riscv/net/bpf_jit_comp64.c
> +++ b/arch/riscv/net/bpf_jit_comp64.c
> @@ -141,6 +141,19 @@ static bool in_auipc_jalr_range(s64 val)
>  		val < ((1L << 31) - (1L << 11));
>  }
>  
> +/* Modify rd pointer to alternate reg to avoid corrupting orignal reg */

Hi Pu Lehui,

nit: original

I suggest running checkpatch --codespell over this series before submitting
v2.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2023-09-16 14:47 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-13 15:34 [PATCH bpf-next 0/6] Zbb support and code simplification for RV64 JIT Pu Lehui
2023-09-13 15:34 ` Pu Lehui
2023-09-13 15:34 ` [PATCH bpf-next 1/6] riscv, bpf: Unify 32-bit sign-extension to emit_sextw Pu Lehui
2023-09-13 15:34   ` Pu Lehui
2023-09-13 15:34 ` [PATCH bpf-next 2/6] riscv, bpf: Unify 32-bit zero-extension to emit_zextw Pu Lehui
2023-09-13 15:34   ` Pu Lehui
2023-09-13 15:34 ` [PATCH bpf-next 3/6] riscv, bpf: Simplify sext and zext logics in branch instructions Pu Lehui
2023-09-13 15:34   ` Pu Lehui
2023-09-16 14:47   ` Simon Horman [this message]
2023-09-16 14:47     ` Simon Horman
2023-09-18  0:32     ` Pu Lehui
2023-09-18  0:32       ` Pu Lehui
2023-09-13 15:34 ` [PATCH bpf-next 4/6] riscv, bpf: Add necessary Zbb instructions Pu Lehui
2023-09-13 15:34   ` Pu Lehui
2023-09-13 16:23   ` Conor Dooley
2023-09-13 16:23     ` Conor Dooley
2023-09-14 13:02     ` Conor Dooley
2023-09-14 13:02       ` Conor Dooley
2023-09-14 14:04       ` Pu Lehui
2023-09-14 14:04         ` Pu Lehui
2023-09-13 15:34 ` [PATCH bpf-next 5/6] riscv, bpf: Optimize sign-extention mov insns with Zbb support Pu Lehui
2023-09-13 15:34   ` Pu Lehui
2023-09-13 15:34 ` [PATCH bpf-next 6/6] riscv, bpf: Optimize bswap " Pu Lehui
2023-09-13 15:34   ` Pu Lehui

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