From: Fan Ni <fan.ni@samsung.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: "Michael Tokarev" <mjt@tls.msk.ru>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"Michael Tsirkin" <mst@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"linuxarm@huawei.com" <linuxarm@huawei.com>
Subject: Re: [PATCH v2 3/4] hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt
Date: Mon, 18 Sep 2023 16:34:49 +0000 [thread overview]
Message-ID: <20230918163441.GA3331103@sjcvldevvm72> (raw)
In-Reply-To: <20230915170418.21337-4-Jonathan.Cameron@huawei.com>
On Fri, Sep 15, 2023 at 06:04:17PM +0100, Jonathan Cameron wrote:
> Done to reduce line lengths where this is used.
> Ext seems sufficiently obvious that it need not be spelt out
> fully.
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Fan Ni <fan.ni@samsung.com>
> include/hw/cxl/cxl_pci.h | 6 ++---
> hw/cxl/cxl-component-utils.c | 49 ++++++++++++++++++++--------------
> hw/pci-bridge/cxl_downstream.c | 2 +-
> hw/pci-bridge/cxl_root_port.c | 2 +-
> hw/pci-bridge/cxl_upstream.c | 2 +-
> 5 files changed, 35 insertions(+), 26 deletions(-)
>
> diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h
> index 407be95b9e..ddf01a543b 100644
> --- a/include/hw/cxl/cxl_pci.h
> +++ b/include/hw/cxl/cxl_pci.h
> @@ -86,7 +86,7 @@ typedef struct CXLDVSECDevice {
> QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice) != 0x38);
>
> /* CXL 2.0 - 8.1.5 (ID 0003) */
> -typedef struct CXLDVSECPortExtensions {
> +typedef struct CXLDVSECPortExt {
> DVSECHeader hdr;
> uint16_t status;
> uint16_t control;
> @@ -100,8 +100,8 @@ typedef struct CXLDVSECPortExtensions {
> uint32_t alt_prefetch_limit_high;
> uint32_t rcrb_base;
> uint32_t rcrb_base_high;
> -} CXLDVSECPortExtensions;
> -QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExtensions) != 0x28);
> +} CXLDVSECPortExt;
> +QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExt) != 0x28);
>
> #define PORT_CONTROL_OFFSET 0xc
> #define PORT_CONTROL_UNMASK_SBR 1
> diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> index 7ef3ef2bd6..c8d632d540 100644
> --- a/hw/cxl/cxl-component-utils.c
> +++ b/hw/cxl/cxl-component-utils.c
> @@ -392,26 +392,35 @@ void cxl_component_create_dvsec(CXLComponentState *cxl,
> case NON_CXL_FUNCTION_MAP_DVSEC:
> break; /* Not yet implemented */
> case EXTENSIONS_PORT_DVSEC:
> - wmask[offset + offsetof(CXLDVSECPortExtensions, control)] = 0x0F;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, control) + 1] = 0x40;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_base)] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_limit)] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base)] = 0xF0;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base) + 1] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit)] = 0xF0;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit) + 1] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)] = 0xF0;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base) + 1] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit)] = 0xF0;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit) + 1] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high)] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 1] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 2] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_high) + 3] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high)] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 1] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 2] = 0xFF;
> - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit_high) + 3] = 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, control)] = 0x0F;
> + wmask[offset + offsetof(CXLDVSECPortExt, control) + 1] = 0x40;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_base)] = 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_limit)] = 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_base)] = 0xF0;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_base) + 1] = 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_limit)] = 0xF0;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_limit) + 1] = 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base)] = 0xF0;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base) + 1] = 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit)] = 0xF0;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit) + 1] =
> + 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high)] =
> + 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) + 1] =
> + 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) + 2] =
> + 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) + 3] =
> + 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high)] =
> + 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) + 1] =
> + 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) + 2] =
> + 0xFF;
> + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) + 3] =
> + 0xFF;
> break;
> case GPF_PORT_DVSEC:
> wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] = 0x0F;
> diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c
> index 54f507318f..cdd79ea1c0 100644
> --- a/hw/pci-bridge/cxl_downstream.c
> +++ b/hw/pci-bridge/cxl_downstream.c
> @@ -98,7 +98,7 @@ static void build_dvsecs(CXLComponentState *cxl)
> {
> uint8_t *dvsec;
>
> - dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ 0 };
> + dvsec = (uint8_t *)&(CXLDVSECPortExt){ 0 };
> cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT,
> EXTENSIONS_PORT_DVSEC_LENGTH,
> EXTENSIONS_PORT_DVSEC,
> diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
> index 7dfd20aa67..8f97697631 100644
> --- a/hw/pci-bridge/cxl_root_port.c
> +++ b/hw/pci-bridge/cxl_root_port.c
> @@ -107,7 +107,7 @@ static void build_dvsecs(CXLComponentState *cxl)
> {
> uint8_t *dvsec;
>
> - dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ 0 };
> + dvsec = (uint8_t *)&(CXLDVSECPortExt){ 0 };
> cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
> EXTENSIONS_PORT_DVSEC_LENGTH,
> EXTENSIONS_PORT_DVSEC,
> diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c
> index a57806fb31..b81bb5fec9 100644
> --- a/hw/pci-bridge/cxl_upstream.c
> +++ b/hw/pci-bridge/cxl_upstream.c
> @@ -116,7 +116,7 @@ static void build_dvsecs(CXLComponentState *cxl)
> {
> uint8_t *dvsec;
>
> - dvsec = (uint8_t *)&(CXLDVSECPortExtensions){
> + dvsec = (uint8_t *)&(CXLDVSECPortExt){
> .status = 0x1, /* Port Power Management Init Complete */
> };
> cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT,
> --
> 2.39.2
>
next prev parent reply other threads:[~2023-09-18 16:35 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-15 17:04 [PATCH v2 0/4] hw/cxl: Line length reduction and related Jonathan Cameron via
2023-09-15 17:04 ` [PATCH v2 1/4] hw/cxl: Use a switch to explicitly check size in caps_reg_read() Jonathan Cameron via
2023-09-18 16:23 ` Fan Ni
2023-09-15 17:04 ` [PATCH v2 2/4] hw/cxl: Use switch statements for read and write of cachemem registers Jonathan Cameron via
2023-09-18 16:32 ` Fan Ni
2023-09-15 17:04 ` [PATCH v2 3/4] hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt Jonathan Cameron via
2023-09-18 16:34 ` Fan Ni [this message]
2023-09-15 17:04 ` [PATCH v2 4/4] hw/cxl: Line length reductions Jonathan Cameron via
2023-09-18 16:48 ` Fan Ni
2023-09-19 9:11 ` Jonathan Cameron via
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230918163441.GA3331103@sjcvldevvm72 \
--to=fan.ni@samsung.com \
--cc=Jonathan.Cameron@huawei.com \
--cc=linuxarm@huawei.com \
--cc=mjt@tls.msk.ru \
--cc=mst@redhat.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.