Re: [RFC v2 6/6] riscv: dts: thead: convert isa detection to new properties

[Conor Dooley <conor@kernel.org>]

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On Tue, Sep 26, 2023 at 11:15:27AM +0800, Icenowy Zheng wrote:
> 在 2023-09-25星期一的 16:59 +0100，Conor Dooley写道：
> > On Sun, Sep 24, 2023 at 07:22:30AM +0800, Icenowy Zheng wrote:
> > > 在 2023-09-22星期五的 09:13 +0100，Conor Dooley写道：
> > > > From: Conor Dooley <conor.dooley@microchip.com>
> > > > 
> > > > Convert the th1520 devicetrees to use the new properties
> > > > "riscv,isa-base" & "riscv,isa-extensions".
> > > > For compatibility with other projects, "riscv,isa" remains.
> > > > 
> > > > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > > > ---
> > > >  arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
> > > >  1 file changed, 12 insertions(+)
> > > > 
> > > > diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi
> > > > b/arch/riscv/boot/dts/thead/th1520.dtsi
> > > > index ce708183b6f6..723f65487246 100644
> > > > --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> > > > +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> > > > @@ -20,6 +20,9 @@ c910_0: cpu@0 {
> > > >                         compatible = "thead,c910", "riscv";
> > > >                         device_type = "cpu";
> > > >                         riscv,isa = "rv64imafdc";
> > > > +                       riscv,isa-base = "rv64i";
> > > > +                       riscv,isa-extensions = "i", "m", "a",
> > > > "f",
> > > > "d", "c", "zicntr", "zicsr",
> > > > +                                              "zifencei",
> > > > "zihpm";
> > > 
> > > Zfh is supported by T-Head C9xx with float too.
> > 
> > You say xx, so just to be sure: Is it always supported, or only with
> > some config for the IP (I wanna know if I need to look out for it
> > while
> > reviewing other SoCs etc)?
> 
> I think it's grouped with FD.
> 
> > Also, do you have a link to the documentation for it? English is the
> > only relevant language I speak, so if the doc is in Chinese, I'll
> > need
> > some help!
> 
> Sorry, but T-Head's official document [1] is only in Chinese. In
> addition, in this document half-float is listed as a "T-Head
> extension", but the encoding matches Zfh. See 15.6 Appendix B-6 Half
> Float (15.6 附录 B-6 浮点半精度指令术语) .

Hmm, I'm not sure that I want to do this. Since it is only an "I think"
and it's not *actually* advertised as being Zfh but apparently has
matching encoding, I would rather someone who is capable of understanding
that document submitted the patch.

> [1]
> https://github.com/T-head-Semi/openc910/blob/main/doc/%E7%8E%84%E9%93%81C910%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C.pdf
> 
> > 
> > > In addition, should X extensions get listed here?
> > 
> > Yes, but someone who cares about documenting these extensions should
> > do
> > it ;)
> 
> Well at least a bunch of Xthead's are now documented.

I meant documented in the dt-binding, not documented in a pdf on GitHub.

> Maybe they will get appended after this patchset get introduced.
> 
> By the way, how to deal with the draft V of C9xx?

Same deal, it'll have to be defined as a vendor extension in the
dt-binding.

Cheers,
Conor.

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