From: Conor Dooley <conor@kernel.org>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-mmc@vger.kernel.org,
William Qiu <william.qiu@starfivetech.com>
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
Emil Renner Berthing <kernel@esmil.dk>,
Rob Herring <robh+dt@kernel.org>,
Jaehoon Chung <jh80.chung@samsung.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: (subset) [PATCH v3 0/3] Change tuning implementation
Date: Sat, 30 Sep 2023 09:59:36 +0100 [thread overview]
Message-ID: <20230930-unmoral-mutiny-e3f91c0dfee9@spud> (raw)
In-Reply-To: <20230922062834.39212-1-william.qiu@starfivetech.com>
From: Conor Dooley <conor.dooley@microchip.com>
On Fri, 22 Sep 2023 14:28:31 +0800, William Qiu wrote:
> This series of patches changes the tuning implementation, from the
> previous way of reading and writing system controller registers to
> reading and writing UHS_REG_EXT register, thus optimizing the tuning
> of obtaining delay-chain.
>
> Changes v2->v3:
> - Rebased to v6.6rc2.
> - Dropped redundant criteria.
> - Keeped "starfive,sysreg" in dts file.
>
> [...]
Applied to riscv-dt-for-next, thanks!
[3/3] riscv: dts: starfive: add assigned-clock* to limit frquency
https://git.kernel.org/conor/c/af571133f7ae
Thanks,
Conor.
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-mmc@vger.kernel.org,
William Qiu <william.qiu@starfivetech.com>
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
Emil Renner Berthing <kernel@esmil.dk>,
Rob Herring <robh+dt@kernel.org>,
Jaehoon Chung <jh80.chung@samsung.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: (subset) [PATCH v3 0/3] Change tuning implementation
Date: Sat, 30 Sep 2023 09:59:36 +0100 [thread overview]
Message-ID: <20230930-unmoral-mutiny-e3f91c0dfee9@spud> (raw)
In-Reply-To: <20230922062834.39212-1-william.qiu@starfivetech.com>
From: Conor Dooley <conor.dooley@microchip.com>
On Fri, 22 Sep 2023 14:28:31 +0800, William Qiu wrote:
> This series of patches changes the tuning implementation, from the
> previous way of reading and writing system controller registers to
> reading and writing UHS_REG_EXT register, thus optimizing the tuning
> of obtaining delay-chain.
>
> Changes v2->v3:
> - Rebased to v6.6rc2.
> - Dropped redundant criteria.
> - Keeped "starfive,sysreg" in dts file.
>
> [...]
Applied to riscv-dt-for-next, thanks!
[3/3] riscv: dts: starfive: add assigned-clock* to limit frquency
https://git.kernel.org/conor/c/af571133f7ae
Thanks,
Conor.
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next prev parent reply other threads:[~2023-09-30 8:59 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-22 6:28 [PATCH v3 0/3] Change tuning implementation William Qiu
2023-09-22 6:28 ` William Qiu
2023-09-22 6:28 ` [PATCH v3 1/3] dt-bindings: mmc: Remove properties from required William Qiu
2023-09-22 6:28 ` William Qiu
2023-09-22 6:28 ` [PATCH v3 2/3] mmc: starfive: Change tuning implementation William Qiu
2023-09-22 6:28 ` William Qiu
2023-09-22 6:28 ` [PATCH v3 3/3] riscv: dts: starfive: add assigned-clock* to limit frquency William Qiu
2023-09-22 6:28 ` William Qiu
2023-09-22 16:36 ` Emil Renner Berthing
2023-09-22 16:36 ` Emil Renner Berthing
2023-09-26 15:03 ` [PATCH v3 0/3] Change tuning implementation Ulf Hansson
2023-09-26 15:03 ` Ulf Hansson
2023-09-30 8:59 ` Conor Dooley [this message]
2023-09-30 8:59 ` (subset) " Conor Dooley
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