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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>,
	Dan Williams <dan.j.williams@intel.com>,
	"Davidlohr Bueso" <dave@stgolabs.net>,
	Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v11 01/20] cxl/port: Fix release of RCD endpoints
Date: Mon, 2 Oct 2023 15:14:43 +0100	[thread overview]
Message-ID: <20231002151443.000017d5@Huawei.com> (raw)
In-Reply-To: <20230927154339.1600738-2-rrichter@amd.com>

On Wed, 27 Sep 2023 17:43:20 +0200
Robert Richter <rrichter@amd.com> wrote:

> Binding and unbindind RCD endpoints (e.g. mem0 device) caused the
> corresponding endpoint not being released. Reason for that is the
> wrong port discovered for RCD endpoints. See cxl_mem_probe() for
> proper endpoint parent detection. Fix delete_endpoint() respectively.
> 
> Signed-off-by: Robert Richter <rrichter@amd.com>

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

I wondered briefly if an access function of some type could be
used to hide this detail away. However it's messy enough that
that is a little tricky so I think we should just keep it
explicit in each location.  So as you have it here.

> ---
>  drivers/cxl/core/port.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 7ca01a834e18..d4572a02989a 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1222,12 +1222,17 @@ static void delete_endpoint(void *data)
>  	struct cxl_memdev *cxlmd = data;
>  	struct cxl_port *endpoint = cxlmd->endpoint;
>  	struct cxl_port *parent_port;
> +	struct cxl_dport *dport;
>  	struct device *parent;
>  
> -	parent_port = cxl_mem_find_port(cxlmd, NULL);
> +	parent_port = cxl_mem_find_port(cxlmd, &dport);
>  	if (!parent_port)
>  		goto out;
> -	parent = &parent_port->dev;
> +
> +	if (dport->rch)
> +		parent = parent_port->uport_dev;
> +	else
> +		parent = &parent_port->dev;
>  
>  	device_lock(parent);
>  	if (parent->driver && !endpoint->dead) {


  reply	other threads:[~2023-10-02 14:14 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-27 15:43 [PATCH v11 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
2023-09-27 15:43 ` [PATCH v11 01/20] cxl/port: Fix release of RCD endpoints Robert Richter
2023-10-02 14:14   ` Jonathan Cameron [this message]
2023-09-27 15:43 ` [PATCH v11 02/20] cxl/core/regs: Rename @dev to @host in struct cxl_register_map Robert Richter
2023-10-02 14:19   ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 03/20] cxl/port: Fix @host confusion in cxl_dport_setup_regs() Robert Richter
2023-10-02 14:32   ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 04/20] cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map Robert Richter
2023-10-02 14:34   ` Jonathan Cameron
2023-10-09 14:27     ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 05/20] cxl/port: Pre-initialize component register mappings Robert Richter
2023-09-27 15:43 ` [PATCH v11 06/20] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Robert Richter
2023-09-27 15:43 ` [PATCH v11 07/20] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Robert Richter
2023-10-02 14:43   ` Jonathan Cameron
2023-10-09 14:35     ` Terry Bowman
2023-10-16 14:09     ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 08/20] cxl/pci: Remove Component Register base address from struct cxl_dev_state Robert Richter
2023-09-27 15:43 ` [PATCH v11 09/20] cxl/port: Remove Component Register base address from struct cxl_port Robert Richter
2023-09-27 15:43 ` [PATCH v11 10/20] cxl/pci: Introduce config option PCIEAER_CXL Robert Richter
2023-10-02 14:46   ` Jonathan Cameron
2023-10-09 14:44     ` Terry Bowman
2023-10-16 13:40       ` Terry Bowman
2023-10-16 14:08         ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 11/20] cxl/pci: Add RCH downstream port AER register discovery Robert Richter
2023-10-02 14:53   ` Jonathan Cameron
2023-10-09 14:55     ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 12/20] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Robert Richter
2023-09-27 15:43   ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 13/20] cxl/pci: Update CXL error logging to use RAS register address Robert Richter
2023-09-27 15:43 ` [PATCH v11 14/20] cxl/pci: Map RCH downstream AER registers for logging protocol errors Robert Richter
2023-10-02 14:56   ` Jonathan Cameron
2023-10-09 14:56     ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 15/20] cxl/pci: Add RCH downstream port error logging Robert Richter
2023-09-27 15:43 ` [PATCH v11 16/20] cxl/pci: Disable root port interrupts in RCH mode Robert Richter
2023-09-27 15:43 ` [PATCH v11 17/20] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Robert Richter
2023-09-27 15:43   ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 18/20] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Robert Richter
2023-09-27 15:43   ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 19/20] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Robert Richter
2023-09-27 15:43 ` [PATCH v11 20/20] cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm Robert Richter
2023-10-02 15:01   ` Jonathan Cameron
2023-09-27 16:04 ` [PATCH v11 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter

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