From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Terry Bowman <terry.bowman@amd.com>
Subject: Re: [PATCH v11 10/20] cxl/pci: Introduce config option PCIEAER_CXL
Date: Mon, 2 Oct 2023 15:46:28 +0100 [thread overview]
Message-ID: <20231002154628.00004f9b@Huawei.com> (raw)
In-Reply-To: <20230927154339.1600738-11-rrichter@amd.com>
On Wed, 27 Sep 2023 17:43:29 +0200
Robert Richter <rrichter@amd.com> wrote:
> CXL error handling depends on AER.
>
> Introduce config option PCIEAER_CXL in preparation of the AER dport
> error handling. Also, introduce the stub function
> devm_cxl_setup_parent_dport() to setup dports.
>
> This is in preparation of follow on patches.
>
> Note the Kconfg part of the option is added in a later patch to enable
> it once coding of the feature is complete.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
Feels like it should just be combined with a later patch that fills
some of this in as on it's own it's just a weird snippet of code :)
Still, one comment inline anyway.
> ---
> drivers/cxl/core/pci.c | 9 +++++++++
> drivers/cxl/cxl.h | 7 +++++++
> drivers/cxl/mem.c | 2 ++
> 3 files changed, 18 insertions(+)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index c7a7887ebdcf..6ba3b7370816 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -718,6 +718,15 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
> return true;
> }
>
> +#ifdef CONFIG_PCIEAER_CXL
> +
> +void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport)
> +{
> +}
> +EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_parent_dport, CXL);
> +
> +#endif
> +
> pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
> pci_channel_state_t state)
> {
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index c07064e0c136..cfa2f6bede41 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -704,6 +704,13 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port,
> struct device *dport_dev, int port_id,
> resource_size_t rcrb);
>
> +#ifdef CONFIG_PCIEAER_CXL
> +void devm_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport);
> +#else
> +static inline void devm_cxl_setup_parent_dport(struct device *host,
> + struct cxl_dport *dport) { }
> +#endif
> +
> struct cxl_decoder *to_cxl_decoder(struct device *dev);
> struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev);
> struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev);
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 04107058739b..61ca21c020fa 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -157,6 +157,8 @@ static int cxl_mem_probe(struct device *dev)
> else
> endpoint_parent = &parent_port->dev;
>
> + devm_cxl_setup_parent_dport(dev, dport);
devm calls can always fail (because if nothing else you have to register
some cleanup and that involves an allocation. If you want to ignore
that I'd expect a comment here.
> +
> device_lock(endpoint_parent);
> if (!endpoint_parent->driver) {
> dev_err(dev, "CXL port topology %s not enabled\n",
next prev parent reply other threads:[~2023-10-02 14:46 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 15:43 [PATCH v11 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
2023-09-27 15:43 ` [PATCH v11 01/20] cxl/port: Fix release of RCD endpoints Robert Richter
2023-10-02 14:14 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 02/20] cxl/core/regs: Rename @dev to @host in struct cxl_register_map Robert Richter
2023-10-02 14:19 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 03/20] cxl/port: Fix @host confusion in cxl_dport_setup_regs() Robert Richter
2023-10-02 14:32 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 04/20] cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map Robert Richter
2023-10-02 14:34 ` Jonathan Cameron
2023-10-09 14:27 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 05/20] cxl/port: Pre-initialize component register mappings Robert Richter
2023-09-27 15:43 ` [PATCH v11 06/20] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Robert Richter
2023-09-27 15:43 ` [PATCH v11 07/20] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Robert Richter
2023-10-02 14:43 ` Jonathan Cameron
2023-10-09 14:35 ` Terry Bowman
2023-10-16 14:09 ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 08/20] cxl/pci: Remove Component Register base address from struct cxl_dev_state Robert Richter
2023-09-27 15:43 ` [PATCH v11 09/20] cxl/port: Remove Component Register base address from struct cxl_port Robert Richter
2023-09-27 15:43 ` [PATCH v11 10/20] cxl/pci: Introduce config option PCIEAER_CXL Robert Richter
2023-10-02 14:46 ` Jonathan Cameron [this message]
2023-10-09 14:44 ` Terry Bowman
2023-10-16 13:40 ` Terry Bowman
2023-10-16 14:08 ` Jonathan Cameron
2023-09-27 15:43 ` [PATCH v11 11/20] cxl/pci: Add RCH downstream port AER register discovery Robert Richter
2023-10-02 14:53 ` Jonathan Cameron
2023-10-09 14:55 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 12/20] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Robert Richter
2023-09-27 15:43 ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 13/20] cxl/pci: Update CXL error logging to use RAS register address Robert Richter
2023-09-27 15:43 ` [PATCH v11 14/20] cxl/pci: Map RCH downstream AER registers for logging protocol errors Robert Richter
2023-10-02 14:56 ` Jonathan Cameron
2023-10-09 14:56 ` Terry Bowman
2023-09-27 15:43 ` [PATCH v11 15/20] cxl/pci: Add RCH downstream port error logging Robert Richter
2023-09-27 15:43 ` [PATCH v11 16/20] cxl/pci: Disable root port interrupts in RCH mode Robert Richter
2023-09-27 15:43 ` [PATCH v11 17/20] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Robert Richter
2023-09-27 15:43 ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 18/20] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Robert Richter
2023-09-27 15:43 ` Robert Richter
2023-09-27 15:43 ` [PATCH v11 19/20] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Robert Richter
2023-09-27 15:43 ` [PATCH v11 20/20] cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm Robert Richter
2023-10-02 15:01 ` Jonathan Cameron
2023-09-27 16:04 ` [PATCH v11 00/20] cxl/pci: Add support for RCH RAS error handling Robert Richter
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