* Re: [PATCH] riscv: dts: starfive: visionfive 2: correct spi's ss pin [not found] <20231011161414.L6wXZVDb@linutronix.de> @ 2023-10-11 19:29 ` Emil Renner Berthing 0 siblings, 0 replies; 4+ messages in thread From: Emil Renner Berthing @ 2023-10-11 19:29 UTC (permalink / raw) To: Nam Cao, kernel, conor, robh+dt, krzysztof.kozlowski+dt, paul.walmsley, palmer, aou, william.qiu, linux-riscv, devicetree, linux-kernel Nam Cao wrote: > The ss pin of spi0 is the same as sck pin. According to the > visionfive 2 documentation, it should be pin 49 instead of 48. Thanks! As far as I can tell this should make the 40pin header match the Raspberry Pi layout, so Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration") > Signed-off-by: Nam Cao <namcao@linuxtronix.de> > --- > arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 12ebe9792356..2c02358abd71 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -431,7 +431,7 @@ GPOEN_ENABLE, > }; > > ss-pins { > - pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS, > + pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS, > GPOEN_ENABLE, > GPI_SYS_SPI0_FSS)>; > bias-disable; > -- > 2.39.2 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] riscv: dts: starfive: visionfive 2: correct spi's ss pin @ 2023-10-11 19:29 ` Emil Renner Berthing 0 siblings, 0 replies; 4+ messages in thread From: Emil Renner Berthing @ 2023-10-11 19:29 UTC (permalink / raw) To: Nam Cao, kernel, conor, robh+dt, krzysztof.kozlowski+dt, paul.walmsley, palmer, aou, william.qiu, linux-riscv, devicetree, linux-kernel Nam Cao wrote: > The ss pin of spi0 is the same as sck pin. According to the > visionfive 2 documentation, it should be pin 49 instead of 48. Thanks! As far as I can tell this should make the 40pin header match the Raspberry Pi layout, so Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > > Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration") > Signed-off-by: Nam Cao <namcao@linuxtronix.de> > --- > arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 12ebe9792356..2c02358abd71 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -431,7 +431,7 @@ GPOEN_ENABLE, > }; > > ss-pins { > - pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS, > + pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS, > GPOEN_ENABLE, > GPI_SYS_SPI0_FSS)>; > bias-disable; > -- > 2.39.2 > ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] riscv: dts: starfive: visionfive 2: correct spi's ss pin 2023-10-11 19:29 ` Emil Renner Berthing @ 2023-10-11 22:32 ` Conor Dooley -1 siblings, 0 replies; 4+ messages in thread From: Conor Dooley @ 2023-10-11 22:32 UTC (permalink / raw) To: Emil Renner Berthing Cc: Nam Cao, kernel, robh+dt, krzysztof.kozlowski+dt, paul.walmsley, palmer, aou, william.qiu, linux-riscv, devicetree, linux-kernel [-- Attachment #1.1: Type: text/plain, Size: 1492 bytes --] Hey, On Wed, Oct 11, 2023 at 12:29:44PM -0700, Emil Renner Berthing wrote: > Nam Cao wrote: > > The ss pin of spi0 is the same as sck pin. According to the > > visionfive 2 documentation, it should be pin 49 instead of 48. > > Thanks! As far as I can tell this should make the 40pin header match the > Raspberry Pi layout, so > > Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> The lists (linux-riscv at least) never got this patch & I cannot find it in my inbox either. Can you send it "properly" please? Thanks, Conor. > > > > > Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration") > > Signed-off-by: Nam Cao <namcao@linuxtronix.de> > > --- > > arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > > index 12ebe9792356..2c02358abd71 100644 > > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > > @@ -431,7 +431,7 @@ GPOEN_ENABLE, > > }; > > > > ss-pins { > > - pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS, > > + pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS, > > GPOEN_ENABLE, > > GPI_SYS_SPI0_FSS)>; > > bias-disable; > > -- > > 2.39.2 > > > [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] riscv: dts: starfive: visionfive 2: correct spi's ss pin @ 2023-10-11 22:32 ` Conor Dooley 0 siblings, 0 replies; 4+ messages in thread From: Conor Dooley @ 2023-10-11 22:32 UTC (permalink / raw) To: Emil Renner Berthing Cc: Nam Cao, kernel, robh+dt, krzysztof.kozlowski+dt, paul.walmsley, palmer, aou, william.qiu, linux-riscv, devicetree, linux-kernel [-- Attachment #1: Type: text/plain, Size: 1492 bytes --] Hey, On Wed, Oct 11, 2023 at 12:29:44PM -0700, Emil Renner Berthing wrote: > Nam Cao wrote: > > The ss pin of spi0 is the same as sck pin. According to the > > visionfive 2 documentation, it should be pin 49 instead of 48. > > Thanks! As far as I can tell this should make the 40pin header match the > Raspberry Pi layout, so > > Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> The lists (linux-riscv at least) never got this patch & I cannot find it in my inbox either. Can you send it "properly" please? Thanks, Conor. > > > > > Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration") > > Signed-off-by: Nam Cao <namcao@linuxtronix.de> > > --- > > arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > > index 12ebe9792356..2c02358abd71 100644 > > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > > @@ -431,7 +431,7 @@ GPOEN_ENABLE, > > }; > > > > ss-pins { > > - pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS, > > + pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS, > > GPOEN_ENABLE, > > GPI_SYS_SPI0_FSS)>; > > bias-disable; > > -- > > 2.39.2 > > > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 4+ messages in thread
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[not found] <20231011161414.L6wXZVDb@linutronix.de>
2023-10-11 19:29 ` [PATCH] riscv: dts: starfive: visionfive 2: correct spi's ss pin Emil Renner Berthing
2023-10-11 19:29 ` Emil Renner Berthing
2023-10-11 22:32 ` Conor Dooley
2023-10-11 22:32 ` Conor Dooley
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