From: Conor Dooley <conor@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Inochi Amaoto <inochiama@outlook.com>,
Chao Wei <chao.wei@sophgo.com>,
Chen Wang <unicorn_wang@outlook.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc
Date: Sat, 14 Oct 2023 10:28:49 +0100 [thread overview]
Message-ID: <20231014-scooter-blurred-995313b571ea@spud> (raw)
In-Reply-To: <ZSpZmsb29ZC5L9dS@xhacker>
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> Maybe this has been discussed before but I didn't find it. I'm wondering
> the reason of adding each plic and clint binding for each SoC, can we
> just use the thead,c900-plic for plic?
> FWICT, arm gic dt usage follows this way, there's no binding for each SoC's
> gic but directly use "arm,gic-v3" and so on.
I'm not aware of why the gic-v3 is done like this, but having different
compatibles allows differentiation between implementations/integrations
of this interrupt controller. I think having that ability is especially
helpful given T-Head have open-sourced a bunch of their IP.
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Inochi Amaoto <inochiama@outlook.com>,
Chao Wei <chao.wei@sophgo.com>,
Chen Wang <unicorn_wang@outlook.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc
Date: Sat, 14 Oct 2023 10:28:49 +0100 [thread overview]
Message-ID: <20231014-scooter-blurred-995313b571ea@spud> (raw)
In-Reply-To: <ZSpZmsb29ZC5L9dS@xhacker>
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> Maybe this has been discussed before but I didn't find it. I'm wondering
> the reason of adding each plic and clint binding for each SoC, can we
> just use the thead,c900-plic for plic?
> FWICT, arm gic dt usage follows this way, there's no binding for each SoC's
> gic but directly use "arm,gic-v3" and so on.
I'm not aware of why the gic-v3 is done like this, but having different
compatibles allows differentiation between implementations/integrations
of this interrupt controller. I think having that ability is especially
helpful given T-Head have open-sourced a bunch of their IP.
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next prev parent reply other threads:[~2023-10-14 9:29 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-09 11:25 [PATCH v2 0/7] Add Huashan Pi board support Inochi Amaoto
2023-10-09 11:25 ` Inochi Amaoto
2023-10-09 11:26 ` [PATCH v2 1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic Inochi Amaoto
2023-10-09 11:26 ` Inochi Amaoto
2023-10-09 11:30 ` Krzysztof Kozlowski
2023-10-09 11:30 ` Krzysztof Kozlowski
[not found] ` <20231009112642.477337-1-inochiama@outlook.com>
2023-10-09 11:26 ` [PATCH v2 2/7] dt-bindings: timer: Add SOPHGO CV1812H clint Inochi Amaoto
2023-10-09 11:26 ` Inochi Amaoto
2023-10-09 11:30 ` Krzysztof Kozlowski
2023-10-09 11:30 ` Krzysztof Kozlowski
2023-10-09 11:26 ` [PATCH v2 3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles Inochi Amaoto
2023-10-09 11:26 ` Inochi Amaoto
2023-10-09 11:30 ` Krzysztof Kozlowski
2023-10-09 11:30 ` Krzysztof Kozlowski
2023-10-09 11:26 ` [PATCH v2 4/7] riscv: dts: sophgo: Separate common devices from cv1800b soc Inochi Amaoto
2023-10-09 11:26 ` Inochi Amaoto
2023-10-12 10:46 ` Chen Wang
2023-10-12 10:46 ` Chen Wang
2023-10-12 12:50 ` Chen Wang
2023-10-12 12:50 ` Chen Wang
2023-10-13 9:08 ` Conor Dooley
2023-10-13 9:08 ` Conor Dooley
2023-10-13 9:50 ` [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree Inochi Amaoto
2023-10-13 9:50 ` Inochi Amaoto
2023-10-13 9:52 ` [PATCH v2 6/7] riscv: dts: sophgo: Separate common devices from cv1800b soc Inochi Amaoto
2023-10-13 9:52 ` Inochi Amaoto
2023-10-13 13:27 ` Conor Dooley
2023-10-13 13:27 ` Conor Dooley
2023-10-13 22:36 ` [PATCH v2 4/7] " Inochi Amaoto
2023-10-13 22:36 ` Inochi Amaoto
2023-10-14 9:04 ` Jisheng Zhang
2023-10-14 9:04 ` Jisheng Zhang
2023-10-14 9:28 ` Conor Dooley [this message]
2023-10-14 9:28 ` Conor Dooley
2023-10-09 11:26 ` [PATCH v2 5/7] riscv: dts: sophgo: cv180x: Add gpio devices Inochi Amaoto
2023-10-09 11:26 ` Inochi Amaoto
2023-10-12 12:52 ` Chen Wang
2023-10-12 12:52 ` Chen Wang
2023-10-09 11:26 ` [PATCH v2 6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree Inochi Amaoto
2023-10-09 11:26 ` Inochi Amaoto
2023-10-10 7:21 ` Chen Wang
2023-10-10 7:21 ` Chen Wang
2023-10-10 7:53 ` Inochi Amaoto
2023-10-10 7:53 ` Inochi Amaoto
2023-10-12 9:41 ` Conor Dooley
2023-10-12 9:41 ` Conor Dooley
2023-10-12 13:02 ` Chen Wang
2023-10-12 13:02 ` Chen Wang
2023-10-09 11:26 ` [PATCH v2 7/7] riscv: dts: sophgo: add Huashan Pi board " Inochi Amaoto
2023-10-09 11:26 ` Inochi Amaoto
2023-10-12 12:53 ` Chen Wang
2023-10-12 12:53 ` Chen Wang
2023-10-12 13:20 ` [PATCH v2 0/7] Add Huashan Pi board support Jisheng Zhang
2023-10-12 13:20 ` Jisheng Zhang
2023-10-13 8:48 ` Krzysztof Kozlowski
2023-10-13 8:48 ` Krzysztof Kozlowski
2023-10-13 8:55 ` Inochi Amaoto
2023-10-13 8:55 ` Inochi Amaoto
2023-10-13 9:00 ` Inochi Amaoto
2023-10-13 9:00 ` Inochi Amaoto
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