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From: Bjorn Helgaas <helgaas@kernel.org>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org,
	bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org, jingoohan1@gmail.com,
	gustavo.pimentel@synopsys.com, mani@kernel.org,
	marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Siddharth Vadapalli <s-vadapalli@ti.com>,
	Ravi Gunasekaran <r-gunasekaran@ti.com>,
	Sriramakrishnan <srk@ti.com>,
	Serge Semin <fancer.lancer@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v24 08/16] PCI: dwc: Disable two BARs to avoid unnecessary memory assignment
Date: Mon, 16 Oct 2023 16:48:26 -0500	[thread overview]
Message-ID: <20231016214826.GA1226689@bhelgaas> (raw)
In-Reply-To: <20231011071423.249458-9-yoshihiro.shimoda.uh@renesas.com>

[+cc Siddharth, Ravi, Sriramakrishnan]

On Wed, Oct 11, 2023 at 04:14:15PM +0900, Yoshihiro Shimoda wrote:
> According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> assignment during device enumeration. Otherwise, Renesas R-Car Gen4
> PCIe controllers cannot work correctly in host mode.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index a7170fd0e847..56cc7ff6d508 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -737,6 +737,14 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
>  	u32 val, ctrl, num_ctrls;
>  	int ret;
>  
> +	/*
> +	 * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> +	 * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> +	 * assignment during device enumeration.
> +	 */
> +	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0);
> +	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0);

I cc'd Siddharth and others because they are working on a Keystone
issue with MSI-X that requires BAR0; see
https://lore.kernel.org/r/20231011123451.34827-1-s-vadapalli@ti.com 

I assume any DWC controller that uses MSI-X would require BAR0 or BAR1
for the MSI-X Table.

I don't have any of the DWC specs and don't know whether any
controllers use MSI-X, so just heads up in case they do.  This patch
was recently merged and will appear in v6.7.

Bjorn

WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: lpieralisi@kernel.org, kw@linux.com, robh@kernel.org,
	bhelgaas@google.com, krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org, jingoohan1@gmail.com,
	gustavo.pimentel@synopsys.com, mani@kernel.org,
	marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	Siddharth Vadapalli <s-vadapalli@ti.com>,
	Ravi Gunasekaran <r-gunasekaran@ti.com>,
	Sriramakrishnan <srk@ti.com>,
	Serge Semin <fancer.lancer@gmail.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v24 08/16] PCI: dwc: Disable two BARs to avoid unnecessary memory assignment
Date: Mon, 16 Oct 2023 16:48:26 -0500	[thread overview]
Message-ID: <20231016214826.GA1226689@bhelgaas> (raw)
In-Reply-To: <20231011071423.249458-9-yoshihiro.shimoda.uh@renesas.com>

[+cc Siddharth, Ravi, Sriramakrishnan]

On Wed, Oct 11, 2023 at 04:14:15PM +0900, Yoshihiro Shimoda wrote:
> According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> assignment during device enumeration. Otherwise, Renesas R-Car Gen4
> PCIe controllers cannot work correctly in host mode.
> 
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index a7170fd0e847..56cc7ff6d508 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -737,6 +737,14 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
>  	u32 val, ctrl, num_ctrls;
>  	int ret;
>  
> +	/*
> +	 * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> +	 * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> +	 * assignment during device enumeration.
> +	 */
> +	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, 0x0);
> +	dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_1, 0x0);

I cc'd Siddharth and others because they are working on a Keystone
issue with MSI-X that requires BAR0; see
https://lore.kernel.org/r/20231011123451.34827-1-s-vadapalli@ti.com 

I assume any DWC controller that uses MSI-X would require BAR0 or BAR1
for the MSI-X Table.

I don't have any of the DWC specs and don't know whether any
controllers use MSI-X, so just heads up in case they do.  This patch
was recently merged and will appear in v6.7.

Bjorn

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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2023-10-16 21:48 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-11  7:14 [PATCH v24 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 01/16] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 02/16] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 03/16] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 04/16] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 05/16] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 06/16] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 07/16] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 08/16] PCI: dwc: Disable two BARs to avoid unnecessary memory assignment Yoshihiro Shimoda
2023-10-11 11:45   ` Serge Semin
2023-10-11 13:07     ` Krzysztof Wilczyński
2023-10-11 13:18       ` Manivannan Sadhasivam
2023-10-11 14:50         ` Serge Semin
2023-10-12  8:03           ` Yoshihiro Shimoda
2023-10-16 21:48   ` Bjorn Helgaas [this message]
2023-10-16 21:48     ` Bjorn Helgaas
2023-10-17  4:39     ` Siddharth Vadapalli
2023-10-17  4:39       ` Siddharth Vadapalli
2023-10-17  9:19   ` Marek Szyprowski
2023-10-17 12:05     ` Yoshihiro Shimoda
2023-10-17 15:16       ` mani
2023-10-18  0:11         ` Yoshihiro Shimoda
2023-10-17 18:58     ` Bjorn Helgaas
2023-10-11  7:14 ` [PATCH v24 09/16] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 11/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 12/16] PCI: Add T_PVPERL macro Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 13/16] PCI: rcar-gen4: Add R-Car Gen4 PCIe controller support for host mode Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 14/16] PCI: rcar-gen4: Add endpoint mode support Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 15/16] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-10-11  7:14 ` [PATCH v24 16/16] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
2023-10-14 21:44 ` [PATCH v24 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Krzysztof Wilczyński

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