[v3, 0/5] riscv: support kernel-mode Vector

[Andy Chiu <andy.chiu@sifive.com>]

This series provides support for running Vector code in kernel mode. The
implementation is based on the v12 series of the Vector series, but with
some additions. First, patch 1, 2 add the kernel-mode Vector patch from
v12 with minor modifications. Then, we introduce a mechanism to defer
restoring Vector context for userspace programs (patch 3). This is
similar to arm64 and x86's approaches when dealing with extra userspace
register context. And it is benefitial to both Vector in user and
kernel-mode. At the end of the series, patch 4, 5 add supports for
making kernel-mode Vector code preemptible. We do this by adding
kernel-mode Vector context, and keeping track of the frame where V
context is last valid. We believe that enabling preemption of running V
is a critical path for getting V more generally available in the
kernel-mode. Besides, with status.VS, we can tell if saving/restoring V
is required. So we don't have to save/restore extra context at each
context switch if registers are not dirty.

The series is tested by loading a kernel module on a PREEMPT kernel.
The module launches multiple kworkers which run Vector operations and
verifies with scalar code. Also, the module provides userspace intefaces
via fops to verify if we can run Vector code on syscall path.

Note: we still have not come to a conclusion on whether a preempitble
kernel-mode simd is a good approach. Also, whether to use the same API
to enable it. I am posting this again to fix known issues and comments
from v2 and provide a to-date reference for who wants to develop
kernel-mode Vector on riscv.

Updated patches (on current order): 1, 3, 4, 5
New patch: -
Unchanged patch: 2
Deleted patch: -

Changelog v3:
 - Rebase on top of riscv for-next (6.6-rc1)
 - Fix a build issue (Conor)
 - Guard vstate_save, vstate_restore with {get,put}_cpu_vector_context.
 - Save V context after disabling preemption. (Guo)
 - Remove irqs_disabled() check from may_use_simd(). (Björn)
 - Comment about nesting V context.

Changelog v2:
 - fix build issues
 - Follow arm's way of starting kernel-mode simd code:
   - add include/asm/simd.h and rename may_use_vector() ->
     may_use_simd()
   - return void in kernel_vector_begin(), and BUG_ON if may_use_simd()
     fails
 - Change naming scheme for functions/macros (Conor):
   - remove KMV
   - 's/rvv/vector/'
   - 's/RISCV_ISA_V_PREEMPTIVE_KMV/RISCV_ISA_V_PREEMPTIVE/'
   - 's/TIF_RISCV_V_KMV/TIF_RISCV_V_KERNEL_MODE/'

Andy Chiu (3):
  riscv: sched: defer restoring Vector context for user
  riscv: vector: do not pass task_struct into
    riscv_v_vstate_{save,restore}()
  riscv: vector: allow kernel-mode Vector with preemption

Greentime Hu (2):
  riscv: Add support for kernel mode vector
  riscv: Add vector extension XOR implementation

 arch/riscv/Kconfig                     |  10 ++
 arch/riscv/include/asm/entry-common.h  |  17 +++
 arch/riscv/include/asm/processor.h     |   2 +
 arch/riscv/include/asm/simd.h          |  56 ++++++++++
 arch/riscv/include/asm/thread_info.h   |   6 +
 arch/riscv/include/asm/vector.h        |  50 +++++++--
 arch/riscv/include/asm/xor.h           |  82 ++++++++++++++
 arch/riscv/kernel/Makefile             |   1 +
 arch/riscv/kernel/asm-offsets.c        |   2 +
 arch/riscv/kernel/entry.S              |  49 ++++++++
 arch/riscv/kernel/kernel_mode_vector.c | 148 +++++++++++++++++++++++++
 arch/riscv/kernel/process.c            |  10 +-
 arch/riscv/kernel/ptrace.c             |   7 +-
 arch/riscv/kernel/signal.c             |   7 +-
 arch/riscv/kernel/vector.c             |   5 +-
 arch/riscv/lib/Makefile                |   1 +
 arch/riscv/lib/xor.S                   |  81 ++++++++++++++
 17 files changed, 516 insertions(+), 18 deletions(-)
 create mode 100644 arch/riscv/include/asm/simd.h
 create mode 100644 arch/riscv/include/asm/xor.h
 create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
 create mode 100644 arch/riscv/lib/xor.S

-- 
2.17.1


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