* [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
@ 2023-10-25 18:56 ` Emil Renner Berthing
0 siblings, 0 replies; 8+ messages in thread
From: Emil Renner Berthing @ 2023-10-25 18:56 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Emil Renner Berthing
This cache controller is also used on the StarFive JH7100 SoC.
Unfortunately it needs a quirk to work properly, so add dedicated
compatible string to be able to match it.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 8a6a78e1a7ab..7e8cebe21584 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -38,7 +38,9 @@ properties:
- sifive,fu740-c000-ccache
- const: cache
- items:
- - const: starfive,jh7110-ccache
+ - enum:
+ - starfive,jh7100-ccache
+ - starfive,jh7110-ccache
- const: sifive,ccache0
- const: cache
- items:
@@ -88,6 +90,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
- microchip,mpfs-ccache
@@ -111,6 +114,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
then:
--
2.40.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
@ 2023-10-25 18:56 ` Emil Renner Berthing
0 siblings, 0 replies; 8+ messages in thread
From: Emil Renner Berthing @ 2023-10-25 18:56 UTC (permalink / raw)
To: linux-riscv, devicetree, linux-kernel
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Emil Renner Berthing
This cache controller is also used on the StarFive JH7100 SoC.
Unfortunately it needs a quirk to work properly, so add dedicated
compatible string to be able to match it.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 8a6a78e1a7ab..7e8cebe21584 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -38,7 +38,9 @@ properties:
- sifive,fu740-c000-ccache
- const: cache
- items:
- - const: starfive,jh7110-ccache
+ - enum:
+ - starfive,jh7100-ccache
+ - starfive,jh7110-ccache
- const: sifive,ccache0
- const: cache
- items:
@@ -88,6 +90,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
- microchip,mpfs-ccache
@@ -111,6 +114,7 @@ allOf:
contains:
enum:
- sifive,fu740-c000-ccache
+ - starfive,jh7100-ccache
- starfive,jh7110-ccache
then:
--
2.40.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
2023-10-25 18:56 ` Emil Renner Berthing
@ 2023-10-26 13:10 ` Conor Dooley
-1 siblings, 0 replies; 8+ messages in thread
From: Conor Dooley @ 2023-10-26 13:10 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley
[-- Attachment #1.1: Type: text/plain, Size: 1728 bytes --]
On Wed, Oct 25, 2023 at 11:56:37AM -0700, Emil Renner Berthing wrote:
> This cache controller is also used on the StarFive JH7100 SoC.
> Unfortunately it needs a quirk to work properly, so add dedicated
> compatible string to be able to match it.
>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
> ---
> Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> index 8a6a78e1a7ab..7e8cebe21584 100644
> --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> @@ -38,7 +38,9 @@ properties:
> - sifive,fu740-c000-ccache
> - const: cache
> - items:
> - - const: starfive,jh7110-ccache
> + - enum:
> + - starfive,jh7100-ccache
> + - starfive,jh7110-ccache
> - const: sifive,ccache0
> - const: cache
> - items:
> @@ -88,6 +90,7 @@ allOf:
> contains:
> enum:
> - sifive,fu740-c000-ccache
> + - starfive,jh7100-ccache
> - starfive,jh7110-ccache
> - microchip,mpfs-ccache
>
> @@ -111,6 +114,7 @@ allOf:
> contains:
> enum:
> - sifive,fu740-c000-ccache
> + - starfive,jh7100-ccache
> - starfive,jh7110-ccache
>
> then:
> --
> 2.40.1
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_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
@ 2023-10-26 13:10 ` Conor Dooley
0 siblings, 0 replies; 8+ messages in thread
From: Conor Dooley @ 2023-10-26 13:10 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-riscv, devicetree, linux-kernel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley
[-- Attachment #1: Type: text/plain, Size: 1728 bytes --]
On Wed, Oct 25, 2023 at 11:56:37AM -0700, Emil Renner Berthing wrote:
> This cache controller is also used on the StarFive JH7100 SoC.
> Unfortunately it needs a quirk to work properly, so add dedicated
> compatible string to be able to match it.
>
> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
> ---
> Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> index 8a6a78e1a7ab..7e8cebe21584 100644
> --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> @@ -38,7 +38,9 @@ properties:
> - sifive,fu740-c000-ccache
> - const: cache
> - items:
> - - const: starfive,jh7110-ccache
> + - enum:
> + - starfive,jh7100-ccache
> + - starfive,jh7110-ccache
> - const: sifive,ccache0
> - const: cache
> - items:
> @@ -88,6 +90,7 @@ allOf:
> contains:
> enum:
> - sifive,fu740-c000-ccache
> + - starfive,jh7100-ccache
> - starfive,jh7110-ccache
> - microchip,mpfs-ccache
>
> @@ -111,6 +114,7 @@ allOf:
> contains:
> enum:
> - sifive,fu740-c000-ccache
> + - starfive,jh7100-ccache
> - starfive,jh7110-ccache
>
> then:
> --
> 2.40.1
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
2023-10-26 13:10 ` Conor Dooley
@ 2023-10-27 18:22 ` Rob Herring
-1 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2023-10-27 18:22 UTC (permalink / raw)
To: Conor Dooley
Cc: Emil Renner Berthing, linux-riscv, devicetree, linux-kernel,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley
On Thu, Oct 26, 2023 at 02:10:37PM +0100, Conor Dooley wrote:
> On Wed, Oct 25, 2023 at 11:56:37AM -0700, Emil Renner Berthing wrote:
> > This cache controller is also used on the StarFive JH7100 SoC.
> > Unfortunately it needs a quirk to work properly, so add dedicated
> > compatible string to be able to match it.
> >
> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Did you want me to pick this up? Or you or Palmer will?
Rob
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
@ 2023-10-27 18:22 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2023-10-27 18:22 UTC (permalink / raw)
To: Conor Dooley
Cc: Emil Renner Berthing, linux-riscv, devicetree, linux-kernel,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley
On Thu, Oct 26, 2023 at 02:10:37PM +0100, Conor Dooley wrote:
> On Wed, Oct 25, 2023 at 11:56:37AM -0700, Emil Renner Berthing wrote:
> > This cache controller is also used on the StarFive JH7100 SoC.
> > Unfortunately it needs a quirk to work properly, so add dedicated
> > compatible string to be able to match it.
> >
> > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Did you want me to pick this up? Or you or Palmer will?
Rob
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
2023-10-27 18:22 ` Rob Herring
@ 2023-10-27 18:38 ` Conor Dooley
-1 siblings, 0 replies; 8+ messages in thread
From: Conor Dooley @ 2023-10-27 18:38 UTC (permalink / raw)
To: Rob Herring
Cc: Emil Renner Berthing, linux-riscv, devicetree, linux-kernel,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley
[-- Attachment #1.1: Type: text/plain, Size: 705 bytes --]
On Fri, Oct 27, 2023 at 01:22:36PM -0500, Rob Herring wrote:
> On Thu, Oct 26, 2023 at 02:10:37PM +0100, Conor Dooley wrote:
> > On Wed, Oct 25, 2023 at 11:56:37AM -0700, Emil Renner Berthing wrote:
> > > This cache controller is also used on the StarFive JH7100 SoC.
> > > Unfortunately it needs a quirk to work properly, so add dedicated
> > > compatible string to be able to match it.
> > >
> > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Did you want me to pick this up? Or you or Palmer will?
Me or Palmer I guess, I was going to take the lot together through soc.
Cheers,
Conor.
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
@ 2023-10-27 18:38 ` Conor Dooley
0 siblings, 0 replies; 8+ messages in thread
From: Conor Dooley @ 2023-10-27 18:38 UTC (permalink / raw)
To: Rob Herring
Cc: Emil Renner Berthing, linux-riscv, devicetree, linux-kernel,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley
[-- Attachment #1: Type: text/plain, Size: 705 bytes --]
On Fri, Oct 27, 2023 at 01:22:36PM -0500, Rob Herring wrote:
> On Thu, Oct 26, 2023 at 02:10:37PM +0100, Conor Dooley wrote:
> > On Wed, Oct 25, 2023 at 11:56:37AM -0700, Emil Renner Berthing wrote:
> > > This cache controller is also used on the StarFive JH7100 SoC.
> > > Unfortunately it needs a quirk to work properly, so add dedicated
> > > compatible string to be able to match it.
> > >
> > > Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Did you want me to pick this up? Or you or Palmer will?
Me or Palmer I guess, I was going to take the lot together through soc.
Cheers,
Conor.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-10-27 18:38 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-25 18:56 [PATCH 1/4] dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible Emil Renner Berthing
2023-10-25 18:56 ` Emil Renner Berthing
2023-10-26 13:10 ` Conor Dooley
2023-10-26 13:10 ` Conor Dooley
2023-10-27 18:22 ` Rob Herring
2023-10-27 18:22 ` Rob Herring
2023-10-27 18:38 ` Conor Dooley
2023-10-27 18:38 ` Conor Dooley
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