From: Conor Dooley <conor@kernel.org>
To: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
Cc: Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] dt-bindings: perf: starfive: Add StarLink PMU
Date: Tue, 14 Nov 2023 17:57:15 +0000 [thread overview]
Message-ID: <20231114-policy-routing-8df2607e76cf@squawk> (raw)
In-Reply-To: <20231114021254.3009799-3-jisheng.teoh@starfivetech.com>
[-- Attachment #1.1: Type: text/plain, Size: 2116 bytes --]
On Tue, Nov 14, 2023 at 10:12:54AM +0800, Ji Sheng Teoh wrote:
> Add device tree binding for StarFive's StarLink PMU (Performance
> Monitor Unit).
>
> Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
> ---
> .../bindings/perf/starfive,starlink-pmu.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/perf/starfive,starlink-pmu.yaml
>
> diff --git a/Documentation/devicetree/bindings/perf/starfive,starlink-pmu.yaml b/Documentation/devicetree/bindings/perf/starfive,starlink-pmu.yaml
> new file mode 100644
> index 000000000000..b164f6849055
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/starfive,starlink-pmu.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/starfive,starlink-pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive StarLink PMU
> +
> +maintainers:
> + - Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
> +
> +description:
> + StarFive's StarLink PMU integrates one or more CPU cores with a shared L3
> + memory system. The PMU support overflow interrupt, up to 16 programmable
> + 64bit event counters, and an independent 64bit cycle counter.
> + StarLink PMU is accessed via MMIO.
> +
> +properties:
> + compatible:
> + const: starfive,starlink-pmu
This compatible (in isolation) is far too generic. Please add a device
specific compatible for the device that has this PMU.
Thanks,
Conor.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + l3_pmu: pmu@12900000 {
> + compatible = "starfive,starlink-pmu";
> + reg = <0x0 0x12900000 0x0 0x10000>;
> + interrupts = <34>;
> + };
> + };
> --
> 2.25.1
>
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
Cc: Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] dt-bindings: perf: starfive: Add StarLink PMU
Date: Tue, 14 Nov 2023 17:57:15 +0000 [thread overview]
Message-ID: <20231114-policy-routing-8df2607e76cf@squawk> (raw)
In-Reply-To: <20231114021254.3009799-3-jisheng.teoh@starfivetech.com>
[-- Attachment #1: Type: text/plain, Size: 2116 bytes --]
On Tue, Nov 14, 2023 at 10:12:54AM +0800, Ji Sheng Teoh wrote:
> Add device tree binding for StarFive's StarLink PMU (Performance
> Monitor Unit).
>
> Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
> ---
> .../bindings/perf/starfive,starlink-pmu.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/perf/starfive,starlink-pmu.yaml
>
> diff --git a/Documentation/devicetree/bindings/perf/starfive,starlink-pmu.yaml b/Documentation/devicetree/bindings/perf/starfive,starlink-pmu.yaml
> new file mode 100644
> index 000000000000..b164f6849055
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/starfive,starlink-pmu.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/perf/starfive,starlink-pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive StarLink PMU
> +
> +maintainers:
> + - Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
> +
> +description:
> + StarFive's StarLink PMU integrates one or more CPU cores with a shared L3
> + memory system. The PMU support overflow interrupt, up to 16 programmable
> + 64bit event counters, and an independent 64bit cycle counter.
> + StarLink PMU is accessed via MMIO.
> +
> +properties:
> + compatible:
> + const: starfive,starlink-pmu
This compatible (in isolation) is far too generic. Please add a device
specific compatible for the device that has this PMU.
Thanks,
Conor.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + l3_pmu: pmu@12900000 {
> + compatible = "starfive,starlink-pmu";
> + reg = <0x0 0x12900000 0x0 0x10000>;
> + interrupts = <34>;
> + };
> + };
> --
> 2.25.1
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2023-11-14 17:57 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-14 2:12 [PATCH v2 0/2] StarFive's StarLink PMU Support Ji Sheng Teoh
2023-11-14 2:12 ` Ji Sheng Teoh
2023-11-14 2:12 ` [PATCH v2 1/2] perf: starfive: Add StarLink PMU support Ji Sheng Teoh
2023-11-14 2:12 ` Ji Sheng Teoh
2023-11-14 2:12 ` [PATCH v2 2/2] dt-bindings: perf: starfive: Add StarLink PMU Ji Sheng Teoh
2023-11-14 2:12 ` Ji Sheng Teoh
2023-11-14 17:57 ` Conor Dooley [this message]
2023-11-14 17:57 ` Conor Dooley
2023-11-15 2:57 ` Ji Sheng Teoh
2023-11-15 2:57 ` Ji Sheng Teoh
-- strict thread matches above, loose matches on Subject: below --
2023-11-14 12:17 [PATCH v2 1/2] perf: starfive: Add StarLink PMU support kernel test robot
2023-11-15 2:02 ` kernel test robot
2023-11-15 2:02 ` kernel test robot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231114-policy-routing-8df2607e76cf@squawk \
--to=conor@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jisheng.teoh@starfivetech.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=leyfoon.tan@starfivetech.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=peterz@infradead.org \
--cc=robh+dt@kernel.org \
--cc=tglx@linutronix.de \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.