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From: Xu Yang <xu.yang_2@nxp.com>
To: frank.li@nxp.com, corbet@lwn.net, shawnguo@kernel.org,
	s.hauer@pengutronix.de, kernel@pengutronix.de, will@kernel.org,
	mark.rutland@arm.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org
Cc: festevam@gmail.com, conor+dt@kernel.org, linux-imx@nxp.com,
	linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
	devicetree@vger.kernel.org, xu.yang_2@nxp.com
Subject: [PATCH v3 5/5] arm64: dts: imx8dxl-ss-ddr: change ddr_pmu0 compatible
Date: Mon, 20 Nov 2023 17:33:17 +0800	[thread overview]
Message-ID: <20231120093317.2652866-5-xu.yang_2@nxp.com> (raw)
In-Reply-To: <20231120093317.2652866-1-xu.yang_2@nxp.com>

i.MX8DXL's ddr pmu has port/channel filter capabilities, but it still is
compatible with "fsl,imx8-ddr-pmu". This will change the compatible.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

---
Changes since v2:
 - fix topo
---
 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
index 550f513708d8..3569abb5bb9b 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
@@ -4,6 +4,6 @@
  */
 
 &ddr_pmu0 {
-	compatible = "fsl,imx8-ddr-pmu";
+	compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu";
 	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 };
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Xu Yang <xu.yang_2@nxp.com>
To: frank.li@nxp.com, corbet@lwn.net, shawnguo@kernel.org,
	s.hauer@pengutronix.de, kernel@pengutronix.de, will@kernel.org,
	mark.rutland@arm.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org
Cc: festevam@gmail.com, conor+dt@kernel.org, linux-imx@nxp.com,
	linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
	devicetree@vger.kernel.org, xu.yang_2@nxp.com
Subject: [PATCH v3 5/5] arm64: dts: imx8dxl-ss-ddr: change ddr_pmu0 compatible
Date: Mon, 20 Nov 2023 17:33:17 +0800	[thread overview]
Message-ID: <20231120093317.2652866-5-xu.yang_2@nxp.com> (raw)
In-Reply-To: <20231120093317.2652866-1-xu.yang_2@nxp.com>

i.MX8DXL's ddr pmu has port/channel filter capabilities, but it still is
compatible with "fsl,imx8-ddr-pmu". This will change the compatible.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

---
Changes since v2:
 - fix topo
---
 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
index 550f513708d8..3569abb5bb9b 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
@@ -4,6 +4,6 @@
  */
 
 &ddr_pmu0 {
-	compatible = "fsl,imx8-ddr-pmu";
+	compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu";
 	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 };
-- 
2.34.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2023-11-20  9:28 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-20  9:33 [PATCH v3 1/5] perf: fsl_imx8_ddr: Add AXI ID PORT CHANNEL filter support Xu Yang
2023-11-20  9:33 ` Xu Yang
2023-11-20  9:33 ` [PATCH v3 2/5] docs/perf: Add explanation for DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk Xu Yang
2023-11-20  9:33   ` Xu Yang
2023-11-20  9:33 ` [PATCH v3 3/5] dt-bindings: perf: fsl-imx-ddr: Add i.MX8DXL compatible Xu Yang
2023-11-20  9:33   ` Xu Yang
2023-11-20  9:33 ` [PATCH v3 4/5] perf: fsl_imx8_ddr: Add driver support for i.MX8DXL DDR Perf Xu Yang
2023-11-20  9:33   ` Xu Yang
2023-11-20  9:33 ` Xu Yang [this message]
2023-11-20  9:33   ` [PATCH v3 5/5] arm64: dts: imx8dxl-ss-ddr: change ddr_pmu0 compatible Xu Yang
2023-12-06  1:34   ` Shawn Guo
2023-12-06  1:34     ` Shawn Guo
2023-12-05 15:16 ` [PATCH v3 1/5] perf: fsl_imx8_ddr: Add AXI ID PORT CHANNEL filter support Will Deacon
2023-12-05 15:16   ` Will Deacon

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