From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Ard Biesheuvel <ardb@kernel.org>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v2 08/13] arm64: Treat HCR_EL2.E2H as RES1 when ID_AA64MMFR4_EL1.E2H0 is negative
Date: Mon, 20 Nov 2023 12:37:16 +0000 [thread overview]
Message-ID: <20231120123721.851738-9-maz@kernel.org> (raw)
In-Reply-To: <20231120123721.851738-1-maz@kernel.org>
For CPUs that have ID_AA64MMFR4_EL1.E2H0 as negative, it is important
to avoid the boot path that sets HCR_EL2.E2H=0. Fortunately, we
already have this path to cope with fruity CPUs.
Tweak init_el2 to look at ID_AA64MMFR4_EL1.E2H0 first.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kernel/cpufeature.c | 5 ++---
arch/arm64/kernel/head.S | 23 +++++++++++++++--------
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index a733c9a83f83..64a026cc5cec 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -140,7 +140,6 @@ void dump_cpu_features(void)
pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps);
}
-#define __ARM64_EXPAND_RFV(reg, field, val) reg##_##field##_##val
#define __ARM64_MAX_POSITIVE(reg, field) \
((reg##_##field##_SIGNED ? \
BIT(reg##_##field##_WIDTH - 1) : \
@@ -165,7 +164,7 @@ void dump_cpu_features(void)
*/
#define ARM64_CPUID_FIELDS(reg, field, min_value) \
__ARM64_CPUID_FIELDS(reg, field, \
- __ARM64_EXPAND_RFV(reg, field, min_value), \
+ SYS_FIELD_VALUE(reg, field, min_value), \
__ARM64_MAX_POSITIVE(reg, field))
/*
@@ -176,7 +175,7 @@ void dump_cpu_features(void)
#define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \
__ARM64_CPUID_FIELDS(reg, field, \
__ARM64_MIN_NEGATIVE(reg, field), \
- __ARM64_EXPAND_RFV(reg, field, max_value))
+ SYS_FIELD_VALUE(reg, field, max_value))
#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
{ \
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 7b236994f0e1..57e39bc3b2b5 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -584,25 +584,32 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
mov_q x1, INIT_SCTLR_EL1_MMU_OFF
/*
- * Fruity CPUs seem to have HCR_EL2.E2H set to RES1,
- * making it impossible to start in nVHE mode. Is that
- * compliant with the architecture? Absolutely not!
+ * Compliant CPUs advertise their VHE-onlyness with
+ * ID_AA64MMFR4_EL1.E2H0 < 0. HCR_EL2.E2H can be
+ * RES1 in that case.
+ *
+ * Fruity CPUs seem to have HCR_EL2.E2H set to RES1, but
+ * don't advertise it (they predate this relaxation).
*/
+ mrs_s x0, SYS_ID_AA64MMFR4_EL1
+ ubfx x0, x0, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH
+ tbnz x0, #(ID_AA64MMFR4_EL1_E2H0_SHIFT + ID_AA64MMFR4_EL1_E2H0_WIDTH - 1), 1f
+
mrs x0, hcr_el2
and x0, x0, #HCR_E2H
- cbz x0, 1f
-
+ cbz x0, 2f
+1:
/* Set a sane SCTLR_EL1, the VHE way */
pre_disable_mmu_workaround
msr_s SYS_SCTLR_EL12, x1
mov x2, #BOOT_CPU_FLAG_E2H
- b 2f
+ b 3f
-1:
+2:
pre_disable_mmu_workaround
msr sctlr_el1, x1
mov x2, xzr
-2:
+3:
__init_el2_nvhe_prepare_eret
mov w0, #BOOT_CPU_MODE_EL2
--
2.39.2
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Ard Biesheuvel <ardb@kernel.org>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v2 08/13] arm64: Treat HCR_EL2.E2H as RES1 when ID_AA64MMFR4_EL1.E2H0 is negative
Date: Mon, 20 Nov 2023 12:37:16 +0000 [thread overview]
Message-ID: <20231120123721.851738-9-maz@kernel.org> (raw)
In-Reply-To: <20231120123721.851738-1-maz@kernel.org>
For CPUs that have ID_AA64MMFR4_EL1.E2H0 as negative, it is important
to avoid the boot path that sets HCR_EL2.E2H=0. Fortunately, we
already have this path to cope with fruity CPUs.
Tweak init_el2 to look at ID_AA64MMFR4_EL1.E2H0 first.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kernel/cpufeature.c | 5 ++---
arch/arm64/kernel/head.S | 23 +++++++++++++++--------
2 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index a733c9a83f83..64a026cc5cec 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -140,7 +140,6 @@ void dump_cpu_features(void)
pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps);
}
-#define __ARM64_EXPAND_RFV(reg, field, val) reg##_##field##_##val
#define __ARM64_MAX_POSITIVE(reg, field) \
((reg##_##field##_SIGNED ? \
BIT(reg##_##field##_WIDTH - 1) : \
@@ -165,7 +164,7 @@ void dump_cpu_features(void)
*/
#define ARM64_CPUID_FIELDS(reg, field, min_value) \
__ARM64_CPUID_FIELDS(reg, field, \
- __ARM64_EXPAND_RFV(reg, field, min_value), \
+ SYS_FIELD_VALUE(reg, field, min_value), \
__ARM64_MAX_POSITIVE(reg, field))
/*
@@ -176,7 +175,7 @@ void dump_cpu_features(void)
#define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \
__ARM64_CPUID_FIELDS(reg, field, \
__ARM64_MIN_NEGATIVE(reg, field), \
- __ARM64_EXPAND_RFV(reg, field, max_value))
+ SYS_FIELD_VALUE(reg, field, max_value))
#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
{ \
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 7b236994f0e1..57e39bc3b2b5 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -584,25 +584,32 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL)
mov_q x1, INIT_SCTLR_EL1_MMU_OFF
/*
- * Fruity CPUs seem to have HCR_EL2.E2H set to RES1,
- * making it impossible to start in nVHE mode. Is that
- * compliant with the architecture? Absolutely not!
+ * Compliant CPUs advertise their VHE-onlyness with
+ * ID_AA64MMFR4_EL1.E2H0 < 0. HCR_EL2.E2H can be
+ * RES1 in that case.
+ *
+ * Fruity CPUs seem to have HCR_EL2.E2H set to RES1, but
+ * don't advertise it (they predate this relaxation).
*/
+ mrs_s x0, SYS_ID_AA64MMFR4_EL1
+ ubfx x0, x0, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH
+ tbnz x0, #(ID_AA64MMFR4_EL1_E2H0_SHIFT + ID_AA64MMFR4_EL1_E2H0_WIDTH - 1), 1f
+
mrs x0, hcr_el2
and x0, x0, #HCR_E2H
- cbz x0, 1f
-
+ cbz x0, 2f
+1:
/* Set a sane SCTLR_EL1, the VHE way */
pre_disable_mmu_workaround
msr_s SYS_SCTLR_EL12, x1
mov x2, #BOOT_CPU_FLAG_E2H
- b 2f
+ b 3f
-1:
+2:
pre_disable_mmu_workaround
msr sctlr_el1, x1
mov x2, xzr
-2:
+3:
__init_el2_nvhe_prepare_eret
mov w0, #BOOT_CPU_MODE_EL2
--
2.39.2
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next prev parent reply other threads:[~2023-11-20 12:37 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-20 12:37 [PATCH v2 00/13] arm64: Add support for FEAT_E2H0, or lack thereof Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-20 12:37 ` [PATCH v2 01/13] arm64: Add macro to compose a sysreg field value Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-20 12:37 ` [PATCH v2 02/13] arm64: cpufeatures: Correctly handle signed values Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 9:29 ` Suzuki K Poulose
2023-11-22 9:29 ` Suzuki K Poulose
2023-11-22 9:46 ` Marc Zyngier
2023-11-22 9:46 ` Marc Zyngier
2023-11-20 12:37 ` [PATCH v2 03/13] arm64: cpufeature: Correctly display signed override values Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 9:16 ` Suzuki K Poulose
2023-11-22 9:16 ` Suzuki K Poulose
2023-11-20 12:37 ` [PATCH v2 04/13] arm64: sysreg: Add layout for ID_AA64MMFR4_EL1 Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 9:15 ` Suzuki K Poulose
2023-11-22 9:15 ` Suzuki K Poulose
2023-11-20 12:37 ` [PATCH v2 05/13] arm64: cpufeature: Add ID_AA64MMFR4_EL1 handling Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 9:54 ` Suzuki K Poulose
2023-11-22 9:54 ` Suzuki K Poulose
2023-11-20 12:37 ` [PATCH v2 06/13] arm64: cpufeature: Detect E2H0 not being implemented Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 14:04 ` Suzuki K Poulose
2023-11-22 14:04 ` Suzuki K Poulose
2023-11-20 12:37 ` [PATCH v2 07/13] arm64: cpufeature: Detect HCR_EL2.NV1 being RES0 Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 14:07 ` Suzuki K Poulose
2023-11-22 14:07 ` Suzuki K Poulose
2023-11-20 12:37 ` Marc Zyngier [this message]
2023-11-20 12:37 ` [PATCH v2 08/13] arm64: Treat HCR_EL2.E2H as RES1 when ID_AA64MMFR4_EL1.E2H0 is negative Marc Zyngier
2023-11-22 14:11 ` Suzuki K Poulose
2023-11-22 14:11 ` Suzuki K Poulose
2023-11-20 12:37 ` [PATCH v2 09/13] arm64: Add override for ID_AA64MMFR4_EL1.E2H0 Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 14:17 ` Suzuki K Poulose
2023-11-22 14:17 ` Suzuki K Poulose
2023-11-20 12:37 ` [PATCH v2 10/13] arm64: Add MIDR-based override infrastructure Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 17:53 ` Suzuki K Poulose
2023-11-22 17:53 ` Suzuki K Poulose
2023-11-20 12:37 ` [PATCH v2 11/13] arm64: Add MIDR-based overrides for ID_AA64MMFR4_EL1.E2H0 Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 17:55 ` Suzuki K Poulose
2023-11-22 17:55 ` Suzuki K Poulose
2023-11-20 12:37 ` [PATCH v2 12/13] KVM: arm64: Expose ID_AA64MMFR4_EL1 to guests Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 18:01 ` Suzuki K Poulose
2023-11-22 18:01 ` Suzuki K Poulose
2023-11-20 12:37 ` [PATCH v2 13/13] KVM: arm64: Force guest's HCR_EL2.E2H RES1 when NV1 is not implemented Marc Zyngier
2023-11-20 12:37 ` Marc Zyngier
2023-11-22 18:06 ` Suzuki K Poulose
2023-11-22 18:06 ` Suzuki K Poulose
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