From: Rob Herring <robh@kernel.org>
To: Georgi Djakov <quic_c_gdjako@quicinc.com>
Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
devicetree@vger.kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, linux-arm-kernel@lists.infradead.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org, quic_cgoldswo@quicinc.com,
quic_sukadev@quicinc.com, quic_pdaly@quicinc.com,
quic_sudaraja@quicinc.com, djakov@kernel.org
Subject: Re: [PATCH v2 1/6] dt-bindings: iommu: Add Translation Buffer Unit bindings
Date: Mon, 27 Nov 2023 12:13:47 -0600 [thread overview]
Message-ID: <20231127181347.GA1953740-robh@kernel.org> (raw)
In-Reply-To: <20231118042730.2799-2-quic_c_gdjako@quicinc.com>
On Fri, Nov 17, 2023 at 08:27:25PM -0800, Georgi Djakov wrote:
> The "apps_smmu" on the Qualcomm sdm845 platform is an implementation
> of the SMMU-500, that consists of a single TCU (Translation Control
> Unit) and multiple TBUs (Translation Buffer Units). The TCU is already
> being described in the generic SMMU DT schema. Add also bindings for
> the TBUs to describe their properties and resources that needs to be
> managed in order to operate them.
>
> In this DT schema, the TBUs are modelled as child devices of the TCU
> and each of them is described with it's register space, clocks, power
> domains, interconnects etc.
>
> Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
> ---
> .../devicetree/bindings/iommu/arm,smmu.yaml | 25 ++++++
> .../bindings/iommu/qcom,qsmmuv500-tbu.yaml | 89 +++++++++++++++++++
> 2 files changed, 114 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index aa9e1c0895a5..f7f89be5f7a3 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -231,6 +231,18 @@ properties:
> enabled for any given device.
> $ref: /schemas/types.yaml#/definitions/phandle
>
> + '#address-cells':
> + enum: [ 1, 2 ]
> +
> + '#size-cells':
> + enum: [ 1, 2 ]
> +
> + ranges: true
> +
> +patternProperties:
> + "^tbu@[0-9a-f]*":
> + type: object
> +
> required:
> - compatible
> - reg
> @@ -453,6 +465,19 @@ allOf:
> - description: Voter clock required for HLOS SMMU access
> - description: Interface clock required for register access
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: qcom,smmu-500
Doesn't match your example. No failure either, so there's some problem
with your schema. The issue is the tbu@ entry above has no constraint on
child properties. Dropping it would solve the issue. However, having a
TBU is not QCom specific, so that doesn't feel right.
> + then:
> + patternProperties:
> + "^tbu@[0-9a-f]*":
'+' rather than '*' as 1 is the minimum, not 0.
> + $ref: qcom,qsmmuv500-tbu.yaml
> + unevaluatedProperties: false
> + properties:
> + ranges: true
> +
> # Disallow clocks for all other platforms with specific compatibles
> - if:
> properties:
> diff --git a/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
> new file mode 100644
> index 000000000000..4dc9d0ca33c9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
> @@ -0,0 +1,89 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iommu/qcom,qsmmuv500-tbu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm TBU (Translation Buffer Unit)
> +
> +maintainers:
> + - Georgi Djakov <quic_c_gdjako@quicinc.com>
> +
> +description:
> + The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains
> + a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides
> + debug features to trace and trigger debug transactions. There are multiple TBU
> + instances distributes with each client core.
> +
> +properties:
> + $nodename:
> + pattern: "^tbu@[0-9a-f]+$"
Drop. You defined this in the parent already.
> +
> + compatible:
> + const: qcom,qsmmuv500-tbu
> +
> + reg:
> + items:
> + - description: Address and size of the TBU's register space.
> +
> + reg-names:
> + items:
> + - const: base
Not a useful name. Drop.
> +
> + clocks:
> + maxItems: 1
> +
> + interconnects:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + qcom,stream-id-range:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: Stream ID range (address and size) that is assigned by the TBU
> + items:
> + minItems: 2
> + maxItems: 2
Perhaps implementations other than QCom's needs this?
Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Georgi Djakov <quic_c_gdjako@quicinc.com>
Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
devicetree@vger.kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, linux-arm-kernel@lists.infradead.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org, quic_cgoldswo@quicinc.com,
quic_sukadev@quicinc.com, quic_pdaly@quicinc.com,
quic_sudaraja@quicinc.com, djakov@kernel.org
Subject: Re: [PATCH v2 1/6] dt-bindings: iommu: Add Translation Buffer Unit bindings
Date: Mon, 27 Nov 2023 12:13:47 -0600 [thread overview]
Message-ID: <20231127181347.GA1953740-robh@kernel.org> (raw)
In-Reply-To: <20231118042730.2799-2-quic_c_gdjako@quicinc.com>
On Fri, Nov 17, 2023 at 08:27:25PM -0800, Georgi Djakov wrote:
> The "apps_smmu" on the Qualcomm sdm845 platform is an implementation
> of the SMMU-500, that consists of a single TCU (Translation Control
> Unit) and multiple TBUs (Translation Buffer Units). The TCU is already
> being described in the generic SMMU DT schema. Add also bindings for
> the TBUs to describe their properties and resources that needs to be
> managed in order to operate them.
>
> In this DT schema, the TBUs are modelled as child devices of the TCU
> and each of them is described with it's register space, clocks, power
> domains, interconnects etc.
>
> Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
> ---
> .../devicetree/bindings/iommu/arm,smmu.yaml | 25 ++++++
> .../bindings/iommu/qcom,qsmmuv500-tbu.yaml | 89 +++++++++++++++++++
> 2 files changed, 114 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index aa9e1c0895a5..f7f89be5f7a3 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -231,6 +231,18 @@ properties:
> enabled for any given device.
> $ref: /schemas/types.yaml#/definitions/phandle
>
> + '#address-cells':
> + enum: [ 1, 2 ]
> +
> + '#size-cells':
> + enum: [ 1, 2 ]
> +
> + ranges: true
> +
> +patternProperties:
> + "^tbu@[0-9a-f]*":
> + type: object
> +
> required:
> - compatible
> - reg
> @@ -453,6 +465,19 @@ allOf:
> - description: Voter clock required for HLOS SMMU access
> - description: Interface clock required for register access
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: qcom,smmu-500
Doesn't match your example. No failure either, so there's some problem
with your schema. The issue is the tbu@ entry above has no constraint on
child properties. Dropping it would solve the issue. However, having a
TBU is not QCom specific, so that doesn't feel right.
> + then:
> + patternProperties:
> + "^tbu@[0-9a-f]*":
'+' rather than '*' as 1 is the minimum, not 0.
> + $ref: qcom,qsmmuv500-tbu.yaml
> + unevaluatedProperties: false
> + properties:
> + ranges: true
> +
> # Disallow clocks for all other platforms with specific compatibles
> - if:
> properties:
> diff --git a/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
> new file mode 100644
> index 000000000000..4dc9d0ca33c9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml
> @@ -0,0 +1,89 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iommu/qcom,qsmmuv500-tbu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm TBU (Translation Buffer Unit)
> +
> +maintainers:
> + - Georgi Djakov <quic_c_gdjako@quicinc.com>
> +
> +description:
> + The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains
> + a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides
> + debug features to trace and trigger debug transactions. There are multiple TBU
> + instances distributes with each client core.
> +
> +properties:
> + $nodename:
> + pattern: "^tbu@[0-9a-f]+$"
Drop. You defined this in the parent already.
> +
> + compatible:
> + const: qcom,qsmmuv500-tbu
> +
> + reg:
> + items:
> + - description: Address and size of the TBU's register space.
> +
> + reg-names:
> + items:
> + - const: base
Not a useful name. Drop.
> +
> + clocks:
> + maxItems: 1
> +
> + interconnects:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + qcom,stream-id-range:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: Stream ID range (address and size) that is assigned by the TBU
> + items:
> + minItems: 2
> + maxItems: 2
Perhaps implementations other than QCom's needs this?
Rob
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next prev parent reply other threads:[~2023-11-27 18:13 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-18 4:27 [PATCH v2 0/6] Add support for Translation Buffer Units Georgi Djakov
2023-11-18 4:27 ` Georgi Djakov
2023-11-18 4:27 ` [PATCH v2 1/6] dt-bindings: iommu: Add Translation Buffer Unit bindings Georgi Djakov
2023-11-18 4:27 ` Georgi Djakov
2023-11-20 15:36 ` Andrew Halaney
2023-11-20 15:36 ` Andrew Halaney
2023-11-27 18:13 ` Rob Herring [this message]
2023-11-27 18:13 ` Rob Herring
2023-11-30 23:24 ` Georgi Djakov
2023-11-30 23:24 ` Georgi Djakov
2023-11-18 4:27 ` [PATCH v2 2/6] iommu/arm-smmu-qcom: Add support for TBUs Georgi Djakov
2023-11-18 4:27 ` Georgi Djakov
2023-11-18 4:27 ` [PATCH v2 3/6] iommu/arm-smmu-qcom: Add Qualcomm TBU driver Georgi Djakov
2023-11-18 4:27 ` Georgi Djakov
2023-11-18 4:27 ` [PATCH v2 4/6] iommu/arm-smmu: Allow using a threaded handler for context interrupts Georgi Djakov
2023-11-18 4:27 ` Georgi Djakov
2023-11-18 4:27 ` [PATCH v2 5/6] iommu/arm-smmu-qcom: Use a custom context fault handler for sdm845 Georgi Djakov
2023-11-18 4:27 ` Georgi Djakov
2023-11-18 4:27 ` [PATCH v2 6/6] arm64: dts: qcom: sdm845: Add DT nodes for the TBUs Georgi Djakov
2023-11-18 4:27 ` Georgi Djakov
2023-11-18 11:21 ` [PATCH v2 0/6] Add support for Translation Buffer Units Bryan O'Donoghue
2023-11-18 11:21 ` Bryan O'Donoghue
2023-11-30 15:19 ` Georgi Djakov
2023-11-30 15:19 ` Georgi Djakov
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