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From: Adam Ford <aford173@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: aford@beaconembeded.com, Adam Ford <aford173@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 3/3] arm64: dts: imx8mm: Slow default video_pll1 clock rate
Date: Mon, 27 Nov 2023 22:54:15 -0600	[thread overview]
Message-ID: <20231128045415.210682-3-aford173@gmail.com> (raw)
In-Reply-To: <20231128045415.210682-1-aford173@gmail.com>

Since commit 8208181fe536 ("clk: imx: composite-8m:
Add imx8m_divider_determine_rate") the lcdif controller has
had the ability to set the lcdif_pixel rate which propagates
up the tree and sets the video_pll1 rate automatically.

By setting this value low, it will force the recalculation of
video_pll1 to the lowest rate needed by lcdif instead of
dividing a larger clock down to the desired clock speed. This
has the  advantage of being able to lower the video_pll1 rate
from 594MHz to 148.5MHz when operating at 1080p. It can go even
lower when operating at lower resolutions and refresh rates.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a3dae114c20e..669fdd2c54e4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1131,7 +1131,7 @@ lcdif: lcdif@32e00000 {
 				assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
 							 <&clk IMX8MM_SYS_PLL2_1000M>,
 							 <&clk IMX8MM_SYS_PLL1_800M>;
-				assigned-clock-rates = <594000000>, <500000000>, <200000000>;
+				assigned-clock-rates = <24000000>, <500000000>, <200000000>;
 				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
 				status = "disabled";
-- 
2.40.1


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WARNING: multiple messages have this Message-ID (diff)
From: Adam Ford <aford173@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: aford@beaconembeded.com, Adam Ford <aford173@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 3/3] arm64: dts: imx8mm: Slow default video_pll1 clock rate
Date: Mon, 27 Nov 2023 22:54:15 -0600	[thread overview]
Message-ID: <20231128045415.210682-3-aford173@gmail.com> (raw)
In-Reply-To: <20231128045415.210682-1-aford173@gmail.com>

Since commit 8208181fe536 ("clk: imx: composite-8m:
Add imx8m_divider_determine_rate") the lcdif controller has
had the ability to set the lcdif_pixel rate which propagates
up the tree and sets the video_pll1 rate automatically.

By setting this value low, it will force the recalculation of
video_pll1 to the lowest rate needed by lcdif instead of
dividing a larger clock down to the desired clock speed. This
has the  advantage of being able to lower the video_pll1 rate
from 594MHz to 148.5MHz when operating at 1080p. It can go even
lower when operating at lower resolutions and refresh rates.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a3dae114c20e..669fdd2c54e4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1131,7 +1131,7 @@ lcdif: lcdif@32e00000 {
 				assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
 							 <&clk IMX8MM_SYS_PLL2_1000M>,
 							 <&clk IMX8MM_SYS_PLL1_800M>;
-				assigned-clock-rates = <594000000>, <500000000>, <200000000>;
+				assigned-clock-rates = <24000000>, <500000000>, <200000000>;
 				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
 				status = "disabled";
-- 
2.40.1


  parent reply	other threads:[~2023-11-28  4:55 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-28  4:54 [PATCH 1/3] arm64: dts: imx8mm: Simplify mipi_dsi clocks Adam Ford
2023-11-28  4:54 ` Adam Ford
2023-11-28  4:54 ` [PATCH 2/3] arm64: dts: imx8mm: Remove video_pll1 clock rate from clk node Adam Ford
2023-11-28  4:54   ` Adam Ford
2023-11-30 15:46   ` Frieder Schrempf
2023-11-30 15:46     ` Frieder Schrempf
2023-11-28  4:54 ` Adam Ford [this message]
2023-11-28  4:54   ` [PATCH 3/3] arm64: dts: imx8mm: Slow default video_pll1 clock rate Adam Ford
2023-11-30 15:46   ` Frieder Schrempf
2023-11-30 15:46     ` Frieder Schrempf
2023-11-30 15:42 ` [PATCH 1/3] arm64: dts: imx8mm: Simplify mipi_dsi clocks Frieder Schrempf
2023-11-30 15:42   ` Frieder Schrempf
2023-12-06  2:17 ` Shawn Guo
2023-12-06  2:17   ` Shawn Guo

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