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From: Qingfang DENG <dqfext@gmail.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor.dooley@microchip.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] riscv: introduce RISCV_EFFICIENT_UNALIGNED_ACCESS
Date: Tue,  5 Dec 2023 16:39:24 +0800	[thread overview]
Message-ID: <20231205083924.48933-1-dqfext@gmail.com> (raw)
In-Reply-To: <20231203135753.1575-2-jszhang@kernel.org>

Hi,

You may as well remove the -mstrict-align CFLAGS in the Makefile, if
this option is enabled:

--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -108,7 +108,9 @@ KBUILD_AFLAGS_MODULE += $(call as-option,-Wa$(comma)-mno-relax)
 # unaligned accesses.  While unaligned accesses are explicitly allowed in the
 # RISC-V ISA, they're emulated by machine mode traps on all extant
 # architectures.  It's faster to have GCC emit only aligned accesses.
+ifneq ($(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS),y)
 KBUILD_CFLAGS += $(call cc-option,-mstrict-align)
+endif
 
 ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)
 prepare: stack_protector_prepare
-- 

- Qingfang

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Qingfang DENG <dqfext@gmail.com>
To: unlisted-recipients:; (no To-header on input)
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor.dooley@microchip.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] riscv: introduce RISCV_EFFICIENT_UNALIGNED_ACCESS
Date: Tue,  5 Dec 2023 16:39:24 +0800	[thread overview]
Message-ID: <20231205083924.48933-1-dqfext@gmail.com> (raw)
In-Reply-To: <20231203135753.1575-2-jszhang@kernel.org>

Hi,

You may as well remove the -mstrict-align CFLAGS in the Makefile, if
this option is enabled:

--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -108,7 +108,9 @@ KBUILD_AFLAGS_MODULE += $(call as-option,-Wa$(comma)-mno-relax)
 # unaligned accesses.  While unaligned accesses are explicitly allowed in the
 # RISC-V ISA, they're emulated by machine mode traps on all extant
 # architectures.  It's faster to have GCC emit only aligned accesses.
+ifneq ($(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS),y)
 KBUILD_CFLAGS += $(call cc-option,-mstrict-align)
+endif
 
 ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)
 prepare: stack_protector_prepare
-- 

- Qingfang

  parent reply	other threads:[~2023-12-05  8:40 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-03 13:57 [PATCH v2 0/2] riscv: enable EFFICIENT_UNALIGNED_ACCESS and DCACHE_WORD_ACCESS Jisheng Zhang
2023-12-03 13:57 ` Jisheng Zhang
2023-12-03 13:57 ` [PATCH v2 1/2] riscv: introduce RISCV_EFFICIENT_UNALIGNED_ACCESS Jisheng Zhang
2023-12-03 13:57   ` Jisheng Zhang
2023-12-04 19:15   ` Charlie Jenkins
2023-12-04 19:15     ` Charlie Jenkins
2023-12-05  2:14     ` Eric Biggers
2023-12-05  2:14       ` Eric Biggers
2023-12-05 13:53       ` Jisheng Zhang
2023-12-05 13:53         ` Jisheng Zhang
2023-12-05 20:56         ` Charlie Jenkins
2023-12-05 20:56           ` Charlie Jenkins
2023-12-06  0:05           ` Charles Lohr
2023-12-06  0:05             ` Charles Lohr
2023-12-06 16:19             ` Palmer Dabbelt
2023-12-06 16:19               ` Palmer Dabbelt
2023-12-05  8:39   ` Qingfang DENG [this message]
2023-12-05  8:39     ` Qingfang DENG
2023-12-22  5:04     ` Eric Biggers
2023-12-22  5:04       ` Eric Biggers
2023-12-03 13:57 ` [PATCH v2 2/2] riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW Jisheng Zhang
2023-12-03 13:57   ` Jisheng Zhang

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