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From: Fuad Tabba <tabba@google.com>
To: kvmarm@lists.linux.dev
Cc: maz@kernel.org, oliver.upton@linux.dev, james.morse@arm.com,
	 suzuki.poulose@arm.com, yuzenghui@huawei.com,
	catalin.marinas@arm.com,  will@kernel.org, eric.auger@redhat.com,
	jingzhangos@google.com,  joey.gouly@arm.com, tabba@google.com,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 4/6] KVM: arm64: Calculate FGT RES0 Bits
Date: Tue,  5 Dec 2023 10:22:46 +0000	[thread overview]
Message-ID: <20231205102248.1915895-5-tabba@google.com> (raw)
In-Reply-To: <20231205102248.1915895-1-tabba@google.com>

All FGT reserved bits are res0, and they are the ones remaining
after accounting for all defined trap bits. Now that we have full
coverage of the trap bits, calculate the res0 bits based on the
other bits.

No functional change intended.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/kvm_arm.h        | 19 +++++++------------
 arch/arm64/kvm/hyp/include/hyp/switch.h |  2 --
 2 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index b0dc3249d5cd..44bbbb4110d3 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -344,49 +344,44 @@
  * Once we get to a point where the two describe the same thing, we'll
  * merge the definitions. One day.
  */
-#define __HFGRTR_EL2_RES0	BIT(51)
 #define __HFGRTR_EL2_MASK	GENMASK(49, 0)
 #define __HFGRTR_EL2_nMASK	(GENMASK(63, 52) | BIT(50))
+#define __HFGRTR_EL2_RES0	~(__HFGRTR_EL2_MASK | __HFGRTR_EL2_nMASK)
 
-#define __HFGWTR_EL2_RES0	(BIT(51) | BIT(46) | BIT(42) | BIT(40) | \
-				 BIT(28) | GENMASK(26, 25) | BIT(21) | BIT(18) | \
-				 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))
 #define __HFGWTR_EL2_MASK	(GENMASK(49, 47) | GENMASK(45, 43) | \
 				 BIT(41) | GENMASK(39, 29) | BIT(27) | \
 				 GENMASK(24, 22) | GENMASK(20, 19) | \
 				 GENMASK(17, 16) | GENMASK(13, 11) | \
 				 GENMASK(8, 3) | GENMASK(1, 0))
 #define __HFGWTR_EL2_nMASK	(GENMASK(63, 52) | BIT(50))
+#define __HFGWTR_EL2_RES0	~(__HFGWTR_EL2_MASK | __HFGWTR_EL2_nMASK)
 
-#define __HFGITR_EL2_RES0	(BIT(63) | BIT(61))
 #define __HFGITR_EL2_MASK	(BIT(62) | BIT(60) | GENMASK(54, 0))
 #define __HFGITR_EL2_nMASK	GENMASK(59, 55)
+#define __HFGITR_EL2_RES0	~(__HFGITR_EL2_MASK | __HFGITR_EL2_nMASK)
 
-#define __HDFGRTR_EL2_RES0	(BIT(49) | BIT(42) | GENMASK(39, 38) |	\
-				 GENMASK(21, 20) | BIT(8))
 #define __HDFGRTR_EL2_MASK	(BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \
 				 GENMASK(41, 40) | GENMASK(37, 22) | \
 				 GENMASK(19, 9) | GENMASK(7, 0))
 #define __HDFGRTR_EL2_nMASK	GENMASK(62, 59)
+#define __HDFGRTR_EL2_RES0	~(__HDFGRTR_EL2_MASK | __HDFGRTR_EL2_nMASK)
 
-#define __HDFGWTR_EL2_RES0	(BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \
-				 BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \
-				 BIT(22) | BIT(9) | BIT(6))
 #define __HDFGWTR_EL2_MASK	(GENMASK(57, 52) | GENMASK(50, 48) | \
 				 GENMASK(46, 44) | GENMASK(42, 41) | \
 				 GENMASK(37, 35) | GENMASK(33, 31) | \
 				 GENMASK(29, 23) | GENMASK(21, 10) | \
 				 GENMASK(8, 7) | GENMASK(5, 0))
 #define __HDFGWTR_EL2_nMASK	GENMASK(62, 60)
+#define __HDFGWTR_EL2_RES0	~(__HDFGWTR_EL2_MASK | __HDFGWTR_EL2_nMASK)
 
-#define __HAFGRTR_EL2_RES0	(GENMASK(63, 50) | GENMASK(16, 5))
 #define __HAFGRTR_EL2_MASK	(GENMASK(49, 17) | GENMASK(4, 0))
 #define __HAFGRTR_EL2_nMASK	0UL
+#define __HAFGRTR_EL2_RES0	~(__HAFGRTR_EL2_MASK | __HAFGRTR_EL2_nMASK)
 
 /* Similar definitions for HCRX_EL2 */
-#define __HCRX_EL2_RES0         (GENMASK(63, 25) | GENMASK(13, 12))
 #define __HCRX_EL2_MASK		(BIT(6))
 #define __HCRX_EL2_nMASK	(GENMASK(24, 14) | GENMASK(11, 7) | GENMASK(5, 0))
+#define __HCRX_EL2_RES0         ~(__HCRX_EL2_MASK | __HCRX_EL2_nMASK)
 
 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
 #define HPFAR_MASK	(~UL(0xf))
diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 2c6e8cbbd081..bf045dc32996 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -86,8 +86,6 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
 #define CHECK_FGT_MASKS(reg)							\
 	do {									\
 		BUILD_BUG_ON((__ ## reg ## _MASK) & (__ ## reg ## _nMASK));	\
-		BUILD_BUG_ON(~((__ ## reg ## _RES0) ^ (__ ## reg ## _MASK) ^	\
-			       (__ ## reg ## _nMASK)));				\
 	} while(0)
 
 static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
-- 
2.43.0.rc2.451.g8631bc7472-goog


WARNING: multiple messages have this Message-ID (diff)
From: Fuad Tabba <tabba@google.com>
To: kvmarm@lists.linux.dev
Cc: maz@kernel.org, oliver.upton@linux.dev, james.morse@arm.com,
	 suzuki.poulose@arm.com, yuzenghui@huawei.com,
	catalin.marinas@arm.com,  will@kernel.org, eric.auger@redhat.com,
	jingzhangos@google.com,  joey.gouly@arm.com, tabba@google.com,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 4/6] KVM: arm64: Calculate FGT RES0 Bits
Date: Tue,  5 Dec 2023 10:22:46 +0000	[thread overview]
Message-ID: <20231205102248.1915895-5-tabba@google.com> (raw)
In-Reply-To: <20231205102248.1915895-1-tabba@google.com>

All FGT reserved bits are res0, and they are the ones remaining
after accounting for all defined trap bits. Now that we have full
coverage of the trap bits, calculate the res0 bits based on the
other bits.

No functional change intended.

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/kvm_arm.h        | 19 +++++++------------
 arch/arm64/kvm/hyp/include/hyp/switch.h |  2 --
 2 files changed, 7 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index b0dc3249d5cd..44bbbb4110d3 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -344,49 +344,44 @@
  * Once we get to a point where the two describe the same thing, we'll
  * merge the definitions. One day.
  */
-#define __HFGRTR_EL2_RES0	BIT(51)
 #define __HFGRTR_EL2_MASK	GENMASK(49, 0)
 #define __HFGRTR_EL2_nMASK	(GENMASK(63, 52) | BIT(50))
+#define __HFGRTR_EL2_RES0	~(__HFGRTR_EL2_MASK | __HFGRTR_EL2_nMASK)
 
-#define __HFGWTR_EL2_RES0	(BIT(51) | BIT(46) | BIT(42) | BIT(40) | \
-				 BIT(28) | GENMASK(26, 25) | BIT(21) | BIT(18) | \
-				 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))
 #define __HFGWTR_EL2_MASK	(GENMASK(49, 47) | GENMASK(45, 43) | \
 				 BIT(41) | GENMASK(39, 29) | BIT(27) | \
 				 GENMASK(24, 22) | GENMASK(20, 19) | \
 				 GENMASK(17, 16) | GENMASK(13, 11) | \
 				 GENMASK(8, 3) | GENMASK(1, 0))
 #define __HFGWTR_EL2_nMASK	(GENMASK(63, 52) | BIT(50))
+#define __HFGWTR_EL2_RES0	~(__HFGWTR_EL2_MASK | __HFGWTR_EL2_nMASK)
 
-#define __HFGITR_EL2_RES0	(BIT(63) | BIT(61))
 #define __HFGITR_EL2_MASK	(BIT(62) | BIT(60) | GENMASK(54, 0))
 #define __HFGITR_EL2_nMASK	GENMASK(59, 55)
+#define __HFGITR_EL2_RES0	~(__HFGITR_EL2_MASK | __HFGITR_EL2_nMASK)
 
-#define __HDFGRTR_EL2_RES0	(BIT(49) | BIT(42) | GENMASK(39, 38) |	\
-				 GENMASK(21, 20) | BIT(8))
 #define __HDFGRTR_EL2_MASK	(BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \
 				 GENMASK(41, 40) | GENMASK(37, 22) | \
 				 GENMASK(19, 9) | GENMASK(7, 0))
 #define __HDFGRTR_EL2_nMASK	GENMASK(62, 59)
+#define __HDFGRTR_EL2_RES0	~(__HDFGRTR_EL2_MASK | __HDFGRTR_EL2_nMASK)
 
-#define __HDFGWTR_EL2_RES0	(BIT(63) | GENMASK(59, 58) | BIT(51) | BIT(47) | \
-				 BIT(43) | GENMASK(40, 38) | BIT(34) | BIT(30) | \
-				 BIT(22) | BIT(9) | BIT(6))
 #define __HDFGWTR_EL2_MASK	(GENMASK(57, 52) | GENMASK(50, 48) | \
 				 GENMASK(46, 44) | GENMASK(42, 41) | \
 				 GENMASK(37, 35) | GENMASK(33, 31) | \
 				 GENMASK(29, 23) | GENMASK(21, 10) | \
 				 GENMASK(8, 7) | GENMASK(5, 0))
 #define __HDFGWTR_EL2_nMASK	GENMASK(62, 60)
+#define __HDFGWTR_EL2_RES0	~(__HDFGWTR_EL2_MASK | __HDFGWTR_EL2_nMASK)
 
-#define __HAFGRTR_EL2_RES0	(GENMASK(63, 50) | GENMASK(16, 5))
 #define __HAFGRTR_EL2_MASK	(GENMASK(49, 17) | GENMASK(4, 0))
 #define __HAFGRTR_EL2_nMASK	0UL
+#define __HAFGRTR_EL2_RES0	~(__HAFGRTR_EL2_MASK | __HAFGRTR_EL2_nMASK)
 
 /* Similar definitions for HCRX_EL2 */
-#define __HCRX_EL2_RES0         (GENMASK(63, 25) | GENMASK(13, 12))
 #define __HCRX_EL2_MASK		(BIT(6))
 #define __HCRX_EL2_nMASK	(GENMASK(24, 14) | GENMASK(11, 7) | GENMASK(5, 0))
+#define __HCRX_EL2_RES0         ~(__HCRX_EL2_MASK | __HCRX_EL2_nMASK)
 
 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
 #define HPFAR_MASK	(~UL(0xf))
diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h
index 2c6e8cbbd081..bf045dc32996 100644
--- a/arch/arm64/kvm/hyp/include/hyp/switch.h
+++ b/arch/arm64/kvm/hyp/include/hyp/switch.h
@@ -86,8 +86,6 @@ static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
 #define CHECK_FGT_MASKS(reg)							\
 	do {									\
 		BUILD_BUG_ON((__ ## reg ## _MASK) & (__ ## reg ## _nMASK));	\
-		BUILD_BUG_ON(~((__ ## reg ## _RES0) ^ (__ ## reg ## _MASK) ^	\
-			       (__ ## reg ## _nMASK)));				\
 	} while(0)
 
 static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
-- 
2.43.0.rc2.451.g8631bc7472-goog


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  parent reply	other threads:[~2023-12-05 10:23 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-05 10:22 [PATCH v1 0/6] KVM: arm64: Fixes to fine grain traps and pKVM traps Fuad Tabba
2023-12-05 10:22 ` Fuad Tabba
2023-12-05 10:22 ` [PATCH v1 1/6] KVM: arm64: Update and fix FGT register masks Fuad Tabba
2023-12-05 10:22   ` Fuad Tabba
2023-12-05 11:19   ` Marc Zyngier
2023-12-05 11:19     ` Marc Zyngier
2023-12-05 11:48     ` Fuad Tabba
2023-12-05 11:48       ` Fuad Tabba
2023-12-05 10:22 ` [PATCH v1 2/6] KVM: arm64: Add bit masks for HAFGRTR_EL2 Fuad Tabba
2023-12-05 10:22   ` Fuad Tabba
2023-12-05 10:22 ` [PATCH v1 3/6] KVM: arm64: Add build validation for trap mask values Fuad Tabba
2023-12-05 10:22   ` Fuad Tabba
2023-12-05 10:22 ` Fuad Tabba [this message]
2023-12-05 10:22   ` [PATCH v1 4/6] KVM: arm64: Calculate FGT RES0 Bits Fuad Tabba
2023-12-05 10:22 ` [PATCH v1 5/6] KVM: arm64: Trap external trace for protected VMs Fuad Tabba
2023-12-05 10:22   ` Fuad Tabba
2023-12-05 10:22 ` [PATCH v1 6/6] KVM: arm64: Mark features as supported " Fuad Tabba
2023-12-05 10:22   ` Fuad Tabba

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