From: Andrew Jones <ajones@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v3 4/4] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt
Date: Wed, 13 Dec 2023 15:59:45 +0100 [thread overview]
Message-ID: <20231213-3b68f487a41af1e3f3c96cf2@orel> (raw)
In-Reply-To: <20231102120129.11261-5-yongxuan.wang@sifive.com>
On Thu, Nov 02, 2023 at 12:01:25PM +0000, Yong-Xuan Wang wrote:
> Update the get-reg-list test to test the Svadu Extension is available
> for guest OS.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> .../testing/selftests/kvm/riscv/get-reg-list.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 9f99ea42f45f..972538d76f48 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -49,6 +49,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
> + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU:
> return true;
> /* AIA registers are always available when Ssaia can't be disabled */
> case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
> @@ -340,6 +341,7 @@ static const char *isa_ext_id_to_str(__u64 id)
> "KVM_RISCV_ISA_EXT_ZICSR",
> "KVM_RISCV_ISA_EXT_ZIFENCEI",
> "KVM_RISCV_ISA_EXT_ZIHPM",
> + "KVM_RISCV_ISA_EXT_SVADU",
> };
>
> if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
> @@ -700,6 +702,10 @@ static __u64 fp_d_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D,
> };
>
> +static __u64 svadu_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU,
> +};
> +
> #define BASE_SUBLIST \
> {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \
> .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}
> @@ -739,6 +745,9 @@ static __u64 fp_d_regs[] = {
> #define FP_D_REGS_SUBLIST \
> {"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \
> .regs_n = ARRAY_SIZE(fp_d_regs),}
> +#define SVADU_REGS_SUBLIST \
> + {"svadu", .feature = KVM_RISCV_ISA_EXT_SVADU, .regs = svadu_regs, \
> + .regs_n = ARRAY_SIZE(svadu_regs),}
>
> static struct vcpu_reg_list h_config = {
> .sublists = {
> @@ -876,6 +885,14 @@ static struct vcpu_reg_list fp_d_config = {
> },
> };
>
> +static struct vcpu_reg_list svadu_config = {
> + .sublists = {
> + BASE_SUBLIST,
> + SVADU_REGS_SUBLIST,
> + {0},
> + },
> +};
> +
> struct vcpu_reg_list *vcpu_configs[] = {
> &h_config,
> &zicbom_config,
> @@ -894,5 +911,6 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &aia_config,
> &fp_f_config,
> &fp_d_config,
> + &svadu_config,
> };
> int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);
> --
> 2.17.1
>
We should rebase this on [1] since it changes sublist management.
[1] https://lore.kernel.org/all/20231128145357.413321-2-apatel at ventanamicro.com/
Thanks,
drew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
greentime.hu@sifive.com, vincent.chen@sifive.com,
tjytimi@163.com, alex@ghiti.fr, conor.dooley@microchip.com,
Paolo Bonzini <pbonzini@redhat.com>,
Shuah Khan <shuah@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <apatel@ventanamicro.com>,
Atish Patra <atishp@rivosinc.com>,
Haibo Xu <haibo1.xu@intel.com>,
kvm@vger.kernel.org, linux-kselftest@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 4/4] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt
Date: Wed, 13 Dec 2023 15:59:45 +0100 [thread overview]
Message-ID: <20231213-3b68f487a41af1e3f3c96cf2@orel> (raw)
In-Reply-To: <20231102120129.11261-5-yongxuan.wang@sifive.com>
On Thu, Nov 02, 2023 at 12:01:25PM +0000, Yong-Xuan Wang wrote:
> Update the get-reg-list test to test the Svadu Extension is available
> for guest OS.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> .../testing/selftests/kvm/riscv/get-reg-list.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 9f99ea42f45f..972538d76f48 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -49,6 +49,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
> + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU:
> return true;
> /* AIA registers are always available when Ssaia can't be disabled */
> case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
> @@ -340,6 +341,7 @@ static const char *isa_ext_id_to_str(__u64 id)
> "KVM_RISCV_ISA_EXT_ZICSR",
> "KVM_RISCV_ISA_EXT_ZIFENCEI",
> "KVM_RISCV_ISA_EXT_ZIHPM",
> + "KVM_RISCV_ISA_EXT_SVADU",
> };
>
> if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
> @@ -700,6 +702,10 @@ static __u64 fp_d_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D,
> };
>
> +static __u64 svadu_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU,
> +};
> +
> #define BASE_SUBLIST \
> {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \
> .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}
> @@ -739,6 +745,9 @@ static __u64 fp_d_regs[] = {
> #define FP_D_REGS_SUBLIST \
> {"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \
> .regs_n = ARRAY_SIZE(fp_d_regs),}
> +#define SVADU_REGS_SUBLIST \
> + {"svadu", .feature = KVM_RISCV_ISA_EXT_SVADU, .regs = svadu_regs, \
> + .regs_n = ARRAY_SIZE(svadu_regs),}
>
> static struct vcpu_reg_list h_config = {
> .sublists = {
> @@ -876,6 +885,14 @@ static struct vcpu_reg_list fp_d_config = {
> },
> };
>
> +static struct vcpu_reg_list svadu_config = {
> + .sublists = {
> + BASE_SUBLIST,
> + SVADU_REGS_SUBLIST,
> + {0},
> + },
> +};
> +
> struct vcpu_reg_list *vcpu_configs[] = {
> &h_config,
> &zicbom_config,
> @@ -894,5 +911,6 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &aia_config,
> &fp_f_config,
> &fp_d_config,
> + &svadu_config,
> };
> int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);
> --
> 2.17.1
>
We should rebase this on [1] since it changes sublist management.
[1] https://lore.kernel.org/all/20231128145357.413321-2-apatel@ventanamicro.com/
Thanks,
drew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org,
greentime.hu@sifive.com, vincent.chen@sifive.com,
tjytimi@163.com, alex@ghiti.fr, conor.dooley@microchip.com,
Paolo Bonzini <pbonzini@redhat.com>,
Shuah Khan <shuah@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <apatel@ventanamicro.com>,
Atish Patra <atishp@rivosinc.com>,
Haibo Xu <haibo1.xu@intel.com>,
kvm@vger.kernel.org, linux-kselftest@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 4/4] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt
Date: Wed, 13 Dec 2023 15:59:45 +0100 [thread overview]
Message-ID: <20231213-3b68f487a41af1e3f3c96cf2@orel> (raw)
In-Reply-To: <20231102120129.11261-5-yongxuan.wang@sifive.com>
On Thu, Nov 02, 2023 at 12:01:25PM +0000, Yong-Xuan Wang wrote:
> Update the get-reg-list test to test the Svadu Extension is available
> for guest OS.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> .../testing/selftests/kvm/riscv/get-reg-list.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index 9f99ea42f45f..972538d76f48 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -49,6 +49,7 @@ bool filter_reg(__u64 reg)
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI:
> case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM:
> + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU:
> return true;
> /* AIA registers are always available when Ssaia can't be disabled */
> case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
> @@ -340,6 +341,7 @@ static const char *isa_ext_id_to_str(__u64 id)
> "KVM_RISCV_ISA_EXT_ZICSR",
> "KVM_RISCV_ISA_EXT_ZIFENCEI",
> "KVM_RISCV_ISA_EXT_ZIHPM",
> + "KVM_RISCV_ISA_EXT_SVADU",
> };
>
> if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) {
> @@ -700,6 +702,10 @@ static __u64 fp_d_regs[] = {
> KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D,
> };
>
> +static __u64 svadu_regs[] = {
> + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVADU,
> +};
> +
> #define BASE_SUBLIST \
> {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \
> .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}
> @@ -739,6 +745,9 @@ static __u64 fp_d_regs[] = {
> #define FP_D_REGS_SUBLIST \
> {"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \
> .regs_n = ARRAY_SIZE(fp_d_regs),}
> +#define SVADU_REGS_SUBLIST \
> + {"svadu", .feature = KVM_RISCV_ISA_EXT_SVADU, .regs = svadu_regs, \
> + .regs_n = ARRAY_SIZE(svadu_regs),}
>
> static struct vcpu_reg_list h_config = {
> .sublists = {
> @@ -876,6 +885,14 @@ static struct vcpu_reg_list fp_d_config = {
> },
> };
>
> +static struct vcpu_reg_list svadu_config = {
> + .sublists = {
> + BASE_SUBLIST,
> + SVADU_REGS_SUBLIST,
> + {0},
> + },
> +};
> +
> struct vcpu_reg_list *vcpu_configs[] = {
> &h_config,
> &zicbom_config,
> @@ -894,5 +911,6 @@ struct vcpu_reg_list *vcpu_configs[] = {
> &aia_config,
> &fp_f_config,
> &fp_d_config,
> + &svadu_config,
> };
> int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);
> --
> 2.17.1
>
We should rebase this on [1] since it changes sublist management.
[1] https://lore.kernel.org/all/20231128145357.413321-2-apatel@ventanamicro.com/
Thanks,
drew
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next prev parent reply other threads:[~2023-12-13 14:59 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-02 12:01 [PATCH v3 0/4] Add Svadu Extension Support Yong-Xuan Wang
2023-11-02 12:01 ` Yong-Xuan Wang
2023-11-02 12:01 ` [PATCH v3 1/4] RISC-V: Detect and Enable " Yong-Xuan Wang
2023-11-02 12:01 ` Yong-Xuan Wang
2023-11-02 12:01 ` Yong-Xuan Wang
2023-12-13 14:53 ` Andrew Jones
2023-12-13 14:53 ` Andrew Jones
2023-12-13 14:53 ` Andrew Jones
2023-11-02 12:01 ` [PATCH v3 2/4] dt-bindings: riscv: Add Svadu Entry Yong-Xuan Wang
2023-11-02 12:01 ` Yong-Xuan Wang
2023-11-02 12:01 ` Yong-Xuan Wang
2023-11-02 12:01 ` [PATCH v3 3/4] RISC-V: KVM: Add Svadu Extension Support for Guest/VM Yong-Xuan Wang
2023-11-02 12:01 ` Yong-Xuan Wang
2023-11-02 12:01 ` Yong-Xuan Wang
2023-11-02 12:01 ` [PATCH v3 4/4] KVM: riscv: selftests: Add Svadu Extension to get-reg-list testt Yong-Xuan Wang
2023-11-02 12:01 ` Yong-Xuan Wang
2023-11-02 12:01 ` Yong-Xuan Wang
2023-12-13 14:59 ` Andrew Jones [this message]
2023-12-13 14:59 ` Andrew Jones
2023-12-13 14:59 ` Andrew Jones
2023-11-14 15:39 ` [PATCH v3 0/4] Add Svadu Extension Support Conor Dooley
2023-11-14 15:39 ` Conor Dooley
2023-11-21 3:12 ` Yong-Xuan Wang
2023-11-21 3:12 ` Yong-Xuan Wang
2024-05-24 9:18 ` Alexandre Ghiti
2024-05-24 9:18 ` Alexandre Ghiti
2024-05-24 9:44 ` Yong-Xuan Wang
2024-05-24 9:44 ` Yong-Xuan Wang
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