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From: Andrew Jones <ajones@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH v2 0/6] RISC-V: KVM: Make SBI uapi consistent with ISA uapi
Date: Wed, 13 Dec 2023 18:09:52 +0100	[thread overview]
Message-ID: <20231213170951.93453-8-ajones@ventanamicro.com> (raw)

SBI extension UAPI is currently almost the same as the ISA extension
UAPI. This series closes the remaining gap by ensuring when an SBI
extension is not available that its register returns ENOENT when
accessed by userspace. We also drop the SBI multi registers from
get-reg-list (ISA multi registers aren't there either) and make
several improvements to the get-reg-list kselftest.

This series is based on Anup's riscv_kvm_more_exts_v1 branch.

Based on kvm-riscv/riscv_kvm_queue

v2:
 - Rebased on kvm-riscv/riscv_kvm_queue which is based on v6.7-rc5

Thanks,
drew


Andrew Jones (6):
  RISC-V: KVM: Don't add SBI multi regs in get-reg-list
  KVM: riscv: selftests: Drop SBI multi registers
  RISC-V: KVM: Make SBI uapi consistent with ISA uapi
  KVM: riscv: selftests: Add RISCV_SBI_EXT_REG
  KVM: riscv: selftests: Use register subtypes
  RISC-V: KVM: selftests: Treat SBI ext regs like ISA ext regs

 arch/riscv/include/asm/kvm_vcpu_sbi.h         |  10 +-
 arch/riscv/kvm/vcpu_onereg.c                  |  53 ++---
 arch/riscv/kvm/vcpu_sbi.c                     |  75 +++---
 arch/riscv/kvm/vcpu_sbi_replace.c             |   2 +-
 .../selftests/kvm/include/kvm_util_base.h     |   1 +
 .../selftests/kvm/include/riscv/processor.h   |  40 ++--
 .../selftests/kvm/lib/riscv/processor.c       |   4 +-
 .../selftests/kvm/riscv/get-reg-list.c        | 220 +++++++++++++-----
 8 files changed, 254 insertions(+), 151 deletions(-)

-- 
2.43.0



WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org
Cc: anup@brainfault.org, atishp@atishpatra.org, palmer@dabbelt.com,
	haibo1.xu@intel.com
Subject: [PATCH v2 0/6] RISC-V: KVM: Make SBI uapi consistent with ISA uapi
Date: Wed, 13 Dec 2023 18:09:52 +0100	[thread overview]
Message-ID: <20231213170951.93453-8-ajones@ventanamicro.com> (raw)

SBI extension UAPI is currently almost the same as the ISA extension
UAPI. This series closes the remaining gap by ensuring when an SBI
extension is not available that its register returns ENOENT when
accessed by userspace. We also drop the SBI multi registers from
get-reg-list (ISA multi registers aren't there either) and make
several improvements to the get-reg-list kselftest.

This series is based on Anup's riscv_kvm_more_exts_v1 branch.

Based on kvm-riscv/riscv_kvm_queue

v2:
 - Rebased on kvm-riscv/riscv_kvm_queue which is based on v6.7-rc5

Thanks,
drew


Andrew Jones (6):
  RISC-V: KVM: Don't add SBI multi regs in get-reg-list
  KVM: riscv: selftests: Drop SBI multi registers
  RISC-V: KVM: Make SBI uapi consistent with ISA uapi
  KVM: riscv: selftests: Add RISCV_SBI_EXT_REG
  KVM: riscv: selftests: Use register subtypes
  RISC-V: KVM: selftests: Treat SBI ext regs like ISA ext regs

 arch/riscv/include/asm/kvm_vcpu_sbi.h         |  10 +-
 arch/riscv/kvm/vcpu_onereg.c                  |  53 ++---
 arch/riscv/kvm/vcpu_sbi.c                     |  75 +++---
 arch/riscv/kvm/vcpu_sbi_replace.c             |   2 +-
 .../selftests/kvm/include/kvm_util_base.h     |   1 +
 .../selftests/kvm/include/riscv/processor.h   |  40 ++--
 .../selftests/kvm/lib/riscv/processor.c       |   4 +-
 .../selftests/kvm/riscv/get-reg-list.c        | 220 +++++++++++++-----
 8 files changed, 254 insertions(+), 151 deletions(-)

-- 
2.43.0


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             reply	other threads:[~2023-12-13 17:09 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-13 17:09 Andrew Jones [this message]
2023-12-13 17:09 ` [PATCH v2 0/6] RISC-V: KVM: Make SBI uapi consistent with ISA uapi Andrew Jones
2023-12-13 17:09 ` [PATCH v2 1/6] RISC-V: KVM: Don't add SBI multi regs in get-reg-list Andrew Jones
2023-12-13 17:09   ` Andrew Jones
2023-12-13 17:23   ` Anup Patel
2023-12-13 17:23     ` Anup Patel
2023-12-13 17:09 ` [PATCH v2 2/6] KVM: riscv: selftests: Drop SBI multi registers Andrew Jones
2023-12-13 17:09   ` Andrew Jones
2023-12-13 17:24   ` Anup Patel
2023-12-13 17:24     ` Anup Patel
2023-12-13 17:09 ` [PATCH v2 3/6] RISC-V: KVM: Make SBI uapi consistent with ISA uapi Andrew Jones
2023-12-13 17:09   ` Andrew Jones
2023-12-13 17:35   ` Anup Patel
2023-12-13 17:35     ` Anup Patel
2023-12-13 17:09 ` [PATCH v2 4/6] KVM: riscv: selftests: Add RISCV_SBI_EXT_REG Andrew Jones
2023-12-13 17:09   ` Andrew Jones
2023-12-13 17:36   ` Anup Patel
2023-12-13 17:36     ` Anup Patel
2023-12-13 17:09 ` [PATCH v2 5/6] KVM: riscv: selftests: Use register subtypes Andrew Jones
2023-12-13 17:09   ` Andrew Jones
2023-12-13 17:39   ` Anup Patel
2023-12-13 17:39     ` Anup Patel
2023-12-13 17:09 ` [PATCH v2 6/6] RISC-V: KVM: selftests: Treat SBI ext regs like ISA ext regs Andrew Jones
2023-12-13 17:09   ` Andrew Jones
2023-12-13 17:42   ` Anup Patel
2023-12-13 17:42     ` Anup Patel
2023-12-14  5:19 ` [PATCH v2 0/6] RISC-V: KVM: Make SBI uapi consistent with ISA uapi Anup Patel
2023-12-14  5:19   ` Anup Patel

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