From: Adrian Hunter <adrian.hunter@intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Heiko Carstens <hca@linux.ibm.com>,
Thomas Richter <tmricht@linux.ibm.com>,
Hendrik Brueckner <brueckner@linux.ibm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@arm.com>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
Yicong Yang <yangyicong@hisilicon.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Will Deacon <will@kernel.org>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Subject: [PATCH RFC V3 4/4] coresight: Have a stab at support for pause / resume
Date: Fri, 15 Dec 2023 08:42:42 +0200 [thread overview]
Message-ID: <20231215064242.36251-1-adrian.hunter@intel.com> (raw)
In-Reply-To: <20231208172449.35444-5-adrian.hunter@intel.com>
For discussion only, un-tested...
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
Changes in V3:
'mode' -> 'flags' so it at least compiles
.../hwtracing/coresight/coresight-etm-perf.c | 29 ++++++++++++++++---
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 5ca6278baff4..7a69e6417ed4 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -45,6 +45,7 @@ static bool etm_perf_up;
struct etm_ctxt {
struct perf_output_handle handle;
struct etm_event_data *event_data;
+ int pr_allowed;
};
static DEFINE_PER_CPU(struct etm_ctxt, etm_ctxt);
@@ -452,6 +453,13 @@ static void etm_event_start(struct perf_event *event, int flags)
struct list_head *path;
u64 hw_id;
+ if (flags & PERF_EF_RESUME) {
+ if (!READ_ONCE(ctxt->pr_allowed))
+ return;
+ } else if (READ_ONCE(event->aux_paused)) {
+ goto out_pr_allowed;
+ }
+
if (!csdev)
goto fail;
@@ -514,6 +522,8 @@ static void etm_event_start(struct perf_event *event, int flags)
event->hw.state = 0;
/* Save the event_data for this ETM */
ctxt->event_data = event_data;
+out_pr_allowed:
+ WRITE_ONCE(ctxt->pr_allowed, 1);
return;
fail_disable_path:
@@ -530,6 +540,7 @@ static void etm_event_start(struct perf_event *event, int flags)
}
fail:
event->hw.state = PERF_HES_STOPPED;
+ WRITE_ONCE(ctxt->pr_allowed, 0);
return;
}
@@ -543,6 +554,11 @@ static void etm_event_stop(struct perf_event *event, int mode)
struct etm_event_data *event_data;
struct list_head *path;
+ if (mode & PERF_EF_PAUSE && !READ_ONCE(ctxt->pr_allowed))
+ return;
+
+ WRITE_ONCE(ctxt->pr_allowed, 0);
+
/*
* If we still have access to the event_data via handle,
* confirm that we haven't messed up the tracking.
@@ -556,7 +572,7 @@ static void etm_event_stop(struct perf_event *event, int mode)
ctxt->event_data = NULL;
if (event->hw.state == PERF_HES_STOPPED)
- return;
+ goto out_pr_allowed;
/* We must have a valid event_data for a running event */
if (WARN_ON(!event_data))
@@ -627,6 +643,10 @@ static void etm_event_stop(struct perf_event *event, int mode)
/* Disabling the path make its elements available to other sessions */
coresight_disable_path(path);
+
+out_pr_allowed:
+ if (mode & PERF_EF_PAUSE)
+ WRITE_ONCE(ctxt->pr_allowed, 1);
}
static int etm_event_add(struct perf_event *event, int mode)
@@ -634,7 +654,7 @@ static int etm_event_add(struct perf_event *event, int mode)
int ret = 0;
struct hw_perf_event *hwc = &event->hw;
- if (mode & PERF_EF_START) {
+ if (mode & PERF_EF_START && !READ_ONCE(event->aux_paused)) {
etm_event_start(event, 0);
if (hwc->state & PERF_HES_STOPPED)
ret = -EINVAL;
@@ -886,8 +906,9 @@ int __init etm_perf_init(void)
{
int ret;
- etm_pmu.capabilities = (PERF_PMU_CAP_EXCLUSIVE |
- PERF_PMU_CAP_ITRACE);
+ etm_pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE |
+ PERF_PMU_CAP_ITRACE |
+ PERF_PMU_CAP_AUX_PAUSE;
etm_pmu.attr_groups = etm_pmu_attr_groups;
etm_pmu.task_ctx_nr = perf_sw_context;
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Adrian Hunter <adrian.hunter@intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Heiko Carstens <hca@linux.ibm.com>,
Thomas Richter <tmricht@linux.ibm.com>,
Hendrik Brueckner <brueckner@linux.ibm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@arm.com>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
Yicong Yang <yangyicong@hisilicon.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Will Deacon <will@kernel.org>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Subject: [PATCH RFC V3 4/4] coresight: Have a stab at support for pause / resume
Date: Fri, 15 Dec 2023 08:42:42 +0200 [thread overview]
Message-ID: <20231215064242.36251-1-adrian.hunter@intel.com> (raw)
In-Reply-To: <20231208172449.35444-5-adrian.hunter@intel.com>
For discussion only, un-tested...
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
---
Changes in V3:
'mode' -> 'flags' so it at least compiles
.../hwtracing/coresight/coresight-etm-perf.c | 29 ++++++++++++++++---
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
index 5ca6278baff4..7a69e6417ed4 100644
--- a/drivers/hwtracing/coresight/coresight-etm-perf.c
+++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
@@ -45,6 +45,7 @@ static bool etm_perf_up;
struct etm_ctxt {
struct perf_output_handle handle;
struct etm_event_data *event_data;
+ int pr_allowed;
};
static DEFINE_PER_CPU(struct etm_ctxt, etm_ctxt);
@@ -452,6 +453,13 @@ static void etm_event_start(struct perf_event *event, int flags)
struct list_head *path;
u64 hw_id;
+ if (flags & PERF_EF_RESUME) {
+ if (!READ_ONCE(ctxt->pr_allowed))
+ return;
+ } else if (READ_ONCE(event->aux_paused)) {
+ goto out_pr_allowed;
+ }
+
if (!csdev)
goto fail;
@@ -514,6 +522,8 @@ static void etm_event_start(struct perf_event *event, int flags)
event->hw.state = 0;
/* Save the event_data for this ETM */
ctxt->event_data = event_data;
+out_pr_allowed:
+ WRITE_ONCE(ctxt->pr_allowed, 1);
return;
fail_disable_path:
@@ -530,6 +540,7 @@ static void etm_event_start(struct perf_event *event, int flags)
}
fail:
event->hw.state = PERF_HES_STOPPED;
+ WRITE_ONCE(ctxt->pr_allowed, 0);
return;
}
@@ -543,6 +554,11 @@ static void etm_event_stop(struct perf_event *event, int mode)
struct etm_event_data *event_data;
struct list_head *path;
+ if (mode & PERF_EF_PAUSE && !READ_ONCE(ctxt->pr_allowed))
+ return;
+
+ WRITE_ONCE(ctxt->pr_allowed, 0);
+
/*
* If we still have access to the event_data via handle,
* confirm that we haven't messed up the tracking.
@@ -556,7 +572,7 @@ static void etm_event_stop(struct perf_event *event, int mode)
ctxt->event_data = NULL;
if (event->hw.state == PERF_HES_STOPPED)
- return;
+ goto out_pr_allowed;
/* We must have a valid event_data for a running event */
if (WARN_ON(!event_data))
@@ -627,6 +643,10 @@ static void etm_event_stop(struct perf_event *event, int mode)
/* Disabling the path make its elements available to other sessions */
coresight_disable_path(path);
+
+out_pr_allowed:
+ if (mode & PERF_EF_PAUSE)
+ WRITE_ONCE(ctxt->pr_allowed, 1);
}
static int etm_event_add(struct perf_event *event, int mode)
@@ -634,7 +654,7 @@ static int etm_event_add(struct perf_event *event, int mode)
int ret = 0;
struct hw_perf_event *hwc = &event->hw;
- if (mode & PERF_EF_START) {
+ if (mode & PERF_EF_START && !READ_ONCE(event->aux_paused)) {
etm_event_start(event, 0);
if (hwc->state & PERF_HES_STOPPED)
ret = -EINVAL;
@@ -886,8 +906,9 @@ int __init etm_perf_init(void)
{
int ret;
- etm_pmu.capabilities = (PERF_PMU_CAP_EXCLUSIVE |
- PERF_PMU_CAP_ITRACE);
+ etm_pmu.capabilities = PERF_PMU_CAP_EXCLUSIVE |
+ PERF_PMU_CAP_ITRACE |
+ PERF_PMU_CAP_AUX_PAUSE;
etm_pmu.attr_groups = etm_pmu_attr_groups;
etm_pmu.task_ctx_nr = perf_sw_context;
--
2.34.1
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next prev parent reply other threads:[~2023-12-15 6:42 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-08 17:24 [PATCH RFC V2 0/4] perf/core: Add ability for an event to "pause" or "resume" AUX area tracing Adrian Hunter
2023-12-08 17:24 ` Adrian Hunter
2023-12-08 17:24 ` [PATCH RFC V2 1/4] perf/core: Add aux_pause, aux_resume, aux_start_paused Adrian Hunter
2023-12-08 17:24 ` Adrian Hunter
2023-12-19 13:42 ` Arnaldo Carvalho de Melo
2023-12-19 13:42 ` Arnaldo Carvalho de Melo
2023-12-20 15:54 ` James Clark
2023-12-20 15:54 ` James Clark
2023-12-20 16:16 ` Adrian Hunter
2023-12-20 16:16 ` Adrian Hunter
2023-12-21 10:05 ` James Clark
2023-12-21 10:05 ` James Clark
2023-12-20 17:41 ` Suzuki K Poulose
2023-12-20 17:41 ` Suzuki K Poulose
2024-01-05 12:57 ` Adrian Hunter
2024-01-05 12:57 ` Adrian Hunter
2023-12-08 17:24 ` [PATCH RFC V2 2/4] perf/x86/intel/pt: Add support for pause / resume Adrian Hunter
2023-12-08 17:24 ` Adrian Hunter
2023-12-08 17:24 ` [PATCH RFC V2 3/4] perf tools: Add support for AUX area " Adrian Hunter
2023-12-08 17:24 ` Adrian Hunter
2023-12-08 17:24 ` [PATCH RFC V2 4/4] coresight: Have a stab at support for " Adrian Hunter
2023-12-08 17:24 ` Adrian Hunter
2023-12-09 17:52 ` kernel test robot
2023-12-15 6:42 ` Adrian Hunter [this message]
2023-12-15 6:42 ` [PATCH RFC V3 " Adrian Hunter
2023-12-20 15:59 ` James Clark
2023-12-20 15:59 ` James Clark
2024-01-05 12:56 ` Adrian Hunter
2024-01-05 12:56 ` Adrian Hunter
2023-12-19 6:05 ` [PATCH RFC V2 0/4] perf/core: Add ability for an event to "pause" or "resume" AUX area tracing Adrian Hunter
2023-12-19 6:05 ` Adrian Hunter
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