From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
ajones@ventanamicro.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v13 11/26] target/riscv/tcg: add MISA user options hash
Date: Mon, 18 Dec 2023 09:53:19 -0300 [thread overview]
Message-ID: <20231218125334.37184-12-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20231218125334.37184-1-dbarboza@ventanamicro.com>
We already track user choice for multi-letter extensions because we
needed to honor user choice when enabling/disabling extensions during
realize(). We refrained from adding the same mechanism for MISA
extensions since we didn't need it.
Profile support requires tne need to check for user choice for MISA
extensions, so let's add the corresponding hash now. It works like the
existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits
options in the cpu_set_misa_ext_cfg() callback.
Note that we can't re-use the same hash from multi-letter extensions
because that hash uses cpu->cfg offsets as keys, while for MISA
extensions we're using MISA bits as keys.
After adding the user hash in cpu_set_misa_ext_cfg(), setting default
values with object_property_set_bool() in add_misa_properties() will end
up marking the user choice hash with them. Set the default value
manually to avoid it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 83d4dd00cf..2affc1f771 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -34,6 +34,7 @@
/* Hash that stores user set extensions */
static GHashTable *multi_ext_user_opts;
+static GHashTable *misa_ext_user_opts;
static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
{
@@ -802,6 +803,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
return;
}
+ g_hash_table_insert(misa_ext_user_opts,
+ GUINT_TO_POINTER(misa_bit),
+ (gpointer)value);
+
prev_val = env->misa_ext & misa_bit;
if (value == prev_val) {
@@ -873,6 +878,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
*/
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
{
+ CPURISCVState *env = &RISCV_CPU(cpu_obj)->env;
bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
int i;
@@ -893,7 +899,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
NULL, (void *)misa_cfg);
object_property_set_description(cpu_obj, name, desc);
if (use_def_vals) {
- object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
+ if (misa_cfg->enabled) {
+ env->misa_ext |= bit;
+ env->misa_ext_mask |= bit;
+ } else {
+ env->misa_ext &= ~bit;
+ env->misa_ext_mask &= ~bit;
+ }
}
}
}
@@ -1142,6 +1154,7 @@ static void tcg_cpu_instance_init(CPUState *cs)
RISCVCPU *cpu = RISCV_CPU(cs);
Object *obj = OBJECT(cpu);
+ misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
riscv_cpu_add_user_properties(obj);
--
2.43.0
next prev parent reply other threads:[~2023-12-18 12:55 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-18 12:53 [PATCH v13 00/26] riscv: RVA22 profiles support Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 01/26] target/riscv: create TYPE_RISCV_VENDOR_CPU Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 02/26] target/riscv/tcg: do not use "!generic" CPU checks Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 03/26] target/riscv/tcg: update priv_ver on user_set extensions Daniel Henrique Barboza
2024-01-04 4:02 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 04/26] target/riscv: add rv64i CPU Daniel Henrique Barboza
2024-01-04 4:11 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 05/26] target/riscv: add zicbop extension flag Daniel Henrique Barboza
2024-01-04 4:12 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 06/26] target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza
2024-01-04 5:00 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 07/26] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza
2024-01-04 5:13 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 08/26] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 09/26] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 10/26] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2024-01-04 6:19 ` Alistair Francis
2023-12-18 12:53 ` Daniel Henrique Barboza [this message]
2023-12-18 12:53 ` [PATCH v13 12/26] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 13/26] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 14/26] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2024-01-04 6:25 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 15/26] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 16/26] target/riscv/tcg: validate profiles during finalize Daniel Henrique Barboza
2024-01-04 6:27 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 17/26] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Daniel Henrique Barboza
2024-01-04 6:29 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 18/26] target/riscv: add 'rva22u64' CPU Daniel Henrique Barboza
2024-01-04 6:31 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 19/26] target/riscv: implement svade Daniel Henrique Barboza
2024-01-04 22:59 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 20/26] target/riscv: add priv ver restriction to profiles Daniel Henrique Barboza
2024-01-04 23:02 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 21/26] target/riscv/cpu.c: finalize satp_mode earlier Daniel Henrique Barboza
2024-01-04 23:02 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 22/26] target/riscv/cpu.c: add riscv_cpu_is_32bit() Daniel Henrique Barboza
2024-01-04 23:04 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 23/26] target/riscv: add satp_mode profile support Daniel Henrique Barboza
2024-01-04 23:07 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 24/26] target/riscv: add 'parent' in profile description Daniel Henrique Barboza
2024-01-05 2:21 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 25/26] target/riscv: add RVA22S64 profile Daniel Henrique Barboza
2024-01-05 2:24 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 26/26] target/riscv: add rva22s64 cpu Daniel Henrique Barboza
2024-01-05 2:25 ` Alistair Francis
2024-01-02 11:40 ` [PATCH v13 00/26] riscv: RVA22 profiles support Daniel Henrique Barboza
2024-01-02 15:12 ` Andrew Jones
2024-01-05 2:39 ` Alistair Francis
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