All of lore.kernel.org
 help / color / mirror / Atom feed
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	bmeng@tinylab.org, liwei1518@gmail.com,
	zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
	ajones@ventanamicro.com,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v13 13/26] target/riscv/tcg: handle profile MISA bits
Date: Mon, 18 Dec 2023 09:53:21 -0300	[thread overview]
Message-ID: <20231218125334.37184-14-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20231218125334.37184-1-dbarboza@ventanamicro.com>

The profile support is handling multi-letter extensions only. Let's add
support for MISA bits as well.

We'll go through every known MISA bit. If the profile doesn't declare
the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext
and env->misa_ext_mask.

Now that we're setting profile MISA bits, one can use the rv64i CPU to boot
Linux using the following options:

-cpu rv64i,rva22u64=true,rv39=true,s=true,zifencei=true

In the near future, when rva22s64 (where, 's', 'zifencei' and sv39 are
mandatory), is implemented, rv64i will be able to boot Linux loading
rva22s64 and no additional flags.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f8c35ba060..f2e0ce0f3d 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -941,6 +941,27 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
     profile->user_set = true;
     profile->enabled = value;
 
+    for (i = 0; misa_bits[i] != 0; i++) {
+        uint32_t bit = misa_bits[i];
+
+        if  (!(profile->misa_ext & bit)) {
+            continue;
+        }
+
+        if (bit == RVI && !profile->enabled) {
+            /*
+             * Disabling profiles will not disable the base
+             * ISA RV64I.
+             */
+            continue;
+        }
+
+        g_hash_table_insert(misa_ext_user_opts,
+                            GUINT_TO_POINTER(bit),
+                            (gpointer)value);
+        riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
+    }
+
     for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
         ext_offset = profile->ext_offsets[i];
 
-- 
2.43.0



  parent reply	other threads:[~2023-12-18 12:58 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-18 12:53 [PATCH v13 00/26] riscv: RVA22 profiles support Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 01/26] target/riscv: create TYPE_RISCV_VENDOR_CPU Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 02/26] target/riscv/tcg: do not use "!generic" CPU checks Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 03/26] target/riscv/tcg: update priv_ver on user_set extensions Daniel Henrique Barboza
2024-01-04  4:02   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 04/26] target/riscv: add rv64i CPU Daniel Henrique Barboza
2024-01-04  4:11   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 05/26] target/riscv: add zicbop extension flag Daniel Henrique Barboza
2024-01-04  4:12   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 06/26] target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza
2024-01-04  5:00   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 07/26] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza
2024-01-04  5:13   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 08/26] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 09/26] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 10/26] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2024-01-04  6:19   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 11/26] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 12/26] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-12-18 12:53 ` Daniel Henrique Barboza [this message]
2023-12-18 12:53 ` [PATCH v13 14/26] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2024-01-04  6:25   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 15/26] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 16/26] target/riscv/tcg: validate profiles during finalize Daniel Henrique Barboza
2024-01-04  6:27   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 17/26] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Daniel Henrique Barboza
2024-01-04  6:29   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 18/26] target/riscv: add 'rva22u64' CPU Daniel Henrique Barboza
2024-01-04  6:31   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 19/26] target/riscv: implement svade Daniel Henrique Barboza
2024-01-04 22:59   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 20/26] target/riscv: add priv ver restriction to profiles Daniel Henrique Barboza
2024-01-04 23:02   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 21/26] target/riscv/cpu.c: finalize satp_mode earlier Daniel Henrique Barboza
2024-01-04 23:02   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 22/26] target/riscv/cpu.c: add riscv_cpu_is_32bit() Daniel Henrique Barboza
2024-01-04 23:04   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 23/26] target/riscv: add satp_mode profile support Daniel Henrique Barboza
2024-01-04 23:07   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 24/26] target/riscv: add 'parent' in profile description Daniel Henrique Barboza
2024-01-05  2:21   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 25/26] target/riscv: add RVA22S64 profile Daniel Henrique Barboza
2024-01-05  2:24   ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 26/26] target/riscv: add rva22s64 cpu Daniel Henrique Barboza
2024-01-05  2:25   ` Alistair Francis
2024-01-02 11:40 ` [PATCH v13 00/26] riscv: RVA22 profiles support Daniel Henrique Barboza
2024-01-02 15:12   ` Andrew Jones
2024-01-05  2:39 ` Alistair Francis

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20231218125334.37184-14-dbarboza@ventanamicro.com \
    --to=dbarboza@ventanamicro.com \
    --cc=ajones@ventanamicro.com \
    --cc=alistair.francis@wdc.com \
    --cc=bmeng@tinylab.org \
    --cc=liwei1518@gmail.com \
    --cc=palmer@rivosinc.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=zhiwei_liu@linux.alibaba.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.