From: Rob Herring <robh@kernel.org>
To: Gatien Chevallier <gatien.chevallier@foss.st.com>
Cc: Oleksii_Moisieiev@epam.com, gregkh@linuxfoundation.org,
herbert@gondor.apana.org.au, davem@davemloft.net,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
alexandre.torgue@foss.st.com, vkoul@kernel.org, jic23@kernel.org,
olivier.moysan@foss.st.com, arnaud.pouliquen@foss.st.com,
mchehab@kernel.org, fabrice.gasnier@foss.st.com,
andi.shyti@kernel.org, ulf.hansson@linaro.org,
edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
hugues.fruchet@foss.st.com, lee@kernel.org, will@kernel.org,
catalin.marinas@arm.com, arnd@kernel.org,
richardcochran@gmail.com, Frank Rowand <frowand.list@gmail.com>,
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wg@grandegger.com, mkl@pengutronix.de,
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linux-usb@vger.kernel.org
Subject: Re: [PATCH v8 03/13] dt-bindings: bus: document RIFSC
Date: Thu, 21 Dec 2023 15:53:16 -0600 [thread overview]
Message-ID: <20231221215316.GA155023-robh@kernel.org> (raw)
In-Reply-To: <20231212152356.345703-4-gatien.chevallier@foss.st.com>
On Tue, Dec 12, 2023 at 04:23:46PM +0100, Gatien Chevallier wrote:
> Document RIFSC (RIF security controller). RIFSC is a firewall controller
> composed of different kinds of hardware resources.
>
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
>
> Changes in V6:
> - Renamed access-controller to access-controllers
> - Removal of access-control-provider property
> - Removal of access-controller and access-controller-names
> declaration in the patternProperties field. Add
> additionalProperties: true in this field.
>
> Changes in V5:
> - Renamed feature-domain* to access-control*
>
> Changes in V2:
> - Corrected errors highlighted by Rob's robot
> - No longer define the maxItems for the "feature-domains"
> property
> - Fix example (node name, status)
> - Declare "feature-domain-names" as an optional
> property for child nodes
> - Fix description of "feature-domains" property
>
> .../bindings/bus/st,stm32mp25-rifsc.yaml | 96 +++++++++++++++++++
> 1 file changed, 96 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
>
> diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
> new file mode 100644
> index 000000000000..95aa7f04c739
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: STM32 Resource isolation framework security controller
> +
> +maintainers:
> + - Gatien Chevallier <gatien.chevallier@foss.st.com>
> +
> +description: |
> + Resource isolation framework (RIF) is a comprehensive set of hardware blocks
> + designed to enforce and manage isolation of STM32 hardware resources like
> + memory and peripherals.
> +
> + The RIFSC (RIF security controller) is composed of three sets of registers,
> + each managing a specific set of hardware resources:
> + - RISC registers associated with RISUP logic (resource isolation device unit
> + for peripherals), assign all non-RIF aware peripherals to zero, one or
> + any security domains (secure, privilege, compartment).
> + - RIMC registers: associated with RIMU logic (resource isolation master
> + unit), assign all non RIF-aware bus master to one security domain by
> + setting secure, privileged and compartment information on the system bus.
> + Alternatively, the RISUP logic controlling the device port access to a
> + peripheral can assign target bus attributes to this peripheral master port
> + (supported attribute: CID).
> + - RISC registers associated with RISAL logic (resource isolation device unit
> + for address space - Lite version), assign address space subregions to one
> + security domains (secure, privilege, compartment).
> +
> +properties:
> + compatible:
> + contains:
> + const: st,stm32mp25-rifsc
This needs to be exact and include 'simple-bus'. You'll need a custom
'select' with the above to avoid matching all other 'simple-bus' cases.
With that,
Reviewed-by: Rob Herring <robh@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Gatien Chevallier <gatien.chevallier@foss.st.com>
Cc: Oleksii_Moisieiev@epam.com, gregkh@linuxfoundation.org,
herbert@gondor.apana.org.au, davem@davemloft.net,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
alexandre.torgue@foss.st.com, vkoul@kernel.org, jic23@kernel.org,
olivier.moysan@foss.st.com, arnaud.pouliquen@foss.st.com,
mchehab@kernel.org, fabrice.gasnier@foss.st.com,
andi.shyti@kernel.org, ulf.hansson@linaro.org,
edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
hugues.fruchet@foss.st.com, lee@kernel.org, will@kernel.org,
catalin.marinas@arm.com, arnd@kernel.org,
richardcochran@gmail.com, Frank Rowand <frowand.list@gmail.com>,
peng.fan@oss.nxp.com, lars@metafoo.de, rcsekar@samsung.com,
wg@grandegger.com, mkl@pengutronix.de,
linux-crypto@vger.kernel.org, devicetree@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
linux-i2c@vger.kernel.org, linux-iio@vger.kernel.org,
alsa-devel@alsa-project.org, linux-medi a@vger.kernel.org,
linux-mmc@vger.kernel.org, netdev@vger.kernel.org,
linux-phy@lists.infradead.org, linux-serial@vger.kernel.org,
linux-spi@vger.kernel.org, linux-usb@vger.kernel.org
Subject: Re: [PATCH v8 03/13] dt-bindings: bus: document RIFSC
Date: Thu, 21 Dec 2023 15:53:16 -0600 [thread overview]
Message-ID: <20231221215316.GA155023-robh@kernel.org> (raw)
In-Reply-To: <20231212152356.345703-4-gatien.chevallier@foss.st.com>
On Tue, Dec 12, 2023 at 04:23:46PM +0100, Gatien Chevallier wrote:
> Document RIFSC (RIF security controller). RIFSC is a firewall controller
> composed of different kinds of hardware resources.
>
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
>
> Changes in V6:
> - Renamed access-controller to access-controllers
> - Removal of access-control-provider property
> - Removal of access-controller and access-controller-names
> declaration in the patternProperties field. Add
> additionalProperties: true in this field.
>
> Changes in V5:
> - Renamed feature-domain* to access-control*
>
> Changes in V2:
> - Corrected errors highlighted by Rob's robot
> - No longer define the maxItems for the "feature-domains"
> property
> - Fix example (node name, status)
> - Declare "feature-domain-names" as an optional
> property for child nodes
> - Fix description of "feature-domains" property
>
> .../bindings/bus/st,stm32mp25-rifsc.yaml | 96 +++++++++++++++++++
> 1 file changed, 96 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
>
> diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
> new file mode 100644
> index 000000000000..95aa7f04c739
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: STM32 Resource isolation framework security controller
> +
> +maintainers:
> + - Gatien Chevallier <gatien.chevallier@foss.st.com>
> +
> +description: |
> + Resource isolation framework (RIF) is a comprehensive set of hardware blocks
> + designed to enforce and manage isolation of STM32 hardware resources like
> + memory and peripherals.
> +
> + The RIFSC (RIF security controller) is composed of three sets of registers,
> + each managing a specific set of hardware resources:
> + - RISC registers associated with RISUP logic (resource isolation device unit
> + for peripherals), assign all non-RIF aware peripherals to zero, one or
> + any security domains (secure, privilege, compartment).
> + - RIMC registers: associated with RIMU logic (resource isolation master
> + unit), assign all non RIF-aware bus master to one security domain by
> + setting secure, privileged and compartment information on the system bus.
> + Alternatively, the RISUP logic controlling the device port access to a
> + peripheral can assign target bus attributes to this peripheral master port
> + (supported attribute: CID).
> + - RISC registers associated with RISAL logic (resource isolation device unit
> + for address space - Lite version), assign address space subregions to one
> + security domains (secure, privilege, compartment).
> +
> +properties:
> + compatible:
> + contains:
> + const: st,stm32mp25-rifsc
This needs to be exact and include 'simple-bus'. You'll need a custom
'select' with the above to avoid matching all other 'simple-bus' cases.
With that,
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2023-12-21 21:56 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-12 15:23 [PATCH v8 00/13] Introduce STM32 Firewall framework Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` [PATCH v8 01/13] dt-bindings: document generic access controllers Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-21 21:51 ` Rob Herring
2023-12-21 21:51 ` Rob Herring
2023-12-12 15:23 ` [PATCH v8 02/13] dt-bindings: treewide: add access-controllers description Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2024-02-03 20:47 ` Wolfram Sang
2024-02-03 20:47 ` Wolfram Sang
2024-02-03 20:47 ` Wolfram Sang
2023-12-12 15:23 ` [PATCH v8 03/13] dt-bindings: bus: document RIFSC Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-21 21:53 ` Rob Herring [this message]
2023-12-21 21:53 ` Rob Herring
2024-01-05 8:19 ` Gatien CHEVALLIER
2024-01-05 8:19 ` Gatien CHEVALLIER
2024-01-05 8:19 ` Gatien CHEVALLIER
2023-12-12 15:23 ` [PATCH v8 04/13] dt-bindings: bus: document ETZPC Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-21 22:00 ` Rob Herring
2023-12-21 22:00 ` Rob Herring
2023-12-12 15:23 ` [PATCH v8 05/13] firewall: introduce stm32_firewall framework Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` [PATCH v8 06/13] of: property: fw_devlink: Add support for "access-controller" Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-21 22:01 ` Rob Herring
2023-12-21 22:01 ` Rob Herring
2023-12-21 22:01 ` Rob Herring
2023-12-12 15:23 ` [PATCH v8 07/13] bus: rifsc: introduce RIFSC firewall controller driver Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` [PATCH v8 08/13] arm64: dts: st: add RIFSC as an access controller for STM32MP25x boards Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` [PATCH v8 09/13] bus: etzpc: introduce ETZPC firewall controller driver Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` [PATCH v8 10/13] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` [PATCH v8 11/13] ARM: dts: stm32: put ETZPC as an access controller " Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` [PATCH v8 12/13] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` [PATCH v8 13/13] ARM: dts: stm32: put ETZPC as an access controller " Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
2023-12-12 15:23 ` Gatien Chevallier
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