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From: Christoph Hellwig <hch@lst.de>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Maxim Kochetkov <fido_max@inbox.ru>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	robh@kernel.org, mpe@ellerman.id.au, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	Conor Dooley <conor@kernel.org>,
	hch@lst.de
Subject: Re: [PATCH 1/1] riscv: set ARCH_DMA_DEFAULT_COHERENT if RISCV_DMA_NONCOHERENT is not set
Date: Fri, 22 Dec 2023 05:14:28 +0100	[thread overview]
Message-ID: <20231222041428.GA2803@lst.de> (raw)
In-Reply-To: <f31d929c-fa0a-4046-be05-38e92afa5d92@flygoat.com>

On Thu, Dec 21, 2023 at 10:27:33PM +0000, Jiaxun Yang wrote:
>
>
> 在 2023/12/21 20:29, Conor Dooley 写道:
>> + Christoph
>>
>> I don't think this patch is correct. Regardless of whether we support
>> cache management operations, DMA is assumed to be coherent unless
>> peripherals etc are specified to otherwise in DT (or however ACPI deals
>> with that kind of thing).
>>
>> What problem are you trying to solve here?
>>
>> On Thu, Dec 21, 2023 at 09:51:52PM +0300, Maxim Kochetkov wrote:
>>> Not all the RISCV are DMA coherent by default.
>
> Sorry for chime in here.
> IMO if your platform is not coherent by default, just insert 
> "dma-noncoherent"
> at devicetree root node.

Exactly.  ARCH_DMA_DEFAULT_COHERENTis a setting that just says for
a given architecture assumes coherent unless otherwise specified,
which has historically been the case for mips.  Not setting it means
non-coherent unless specified, which has historially been the case
for arm.

RISC-V starte out without support for non-coherent DMA, and high ups
in RISCV still told me in 2019 that RISC-V doesn't need cache
management instructions because no new hardware would ever not be
dma coherent.  Yeah, right..

Anyay, Linux for RISC-V has historically been coherent only and then
coherent default, so this option is wrong, and you need to mark
you platform as non-coherent by inserting dma-noncoherent somewhere.


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WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Maxim Kochetkov <fido_max@inbox.ru>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	robh@kernel.org, mpe@ellerman.id.au, aou@eecs.berkeley.edu,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	Conor Dooley <conor@kernel.org>,
	hch@lst.de
Subject: Re: [PATCH 1/1] riscv: set ARCH_DMA_DEFAULT_COHERENT if RISCV_DMA_NONCOHERENT is not set
Date: Fri, 22 Dec 2023 05:14:28 +0100	[thread overview]
Message-ID: <20231222041428.GA2803@lst.de> (raw)
In-Reply-To: <f31d929c-fa0a-4046-be05-38e92afa5d92@flygoat.com>

On Thu, Dec 21, 2023 at 10:27:33PM +0000, Jiaxun Yang wrote:
>
>
> 在 2023/12/21 20:29, Conor Dooley 写道:
>> + Christoph
>>
>> I don't think this patch is correct. Regardless of whether we support
>> cache management operations, DMA is assumed to be coherent unless
>> peripherals etc are specified to otherwise in DT (or however ACPI deals
>> with that kind of thing).
>>
>> What problem are you trying to solve here?
>>
>> On Thu, Dec 21, 2023 at 09:51:52PM +0300, Maxim Kochetkov wrote:
>>> Not all the RISCV are DMA coherent by default.
>
> Sorry for chime in here.
> IMO if your platform is not coherent by default, just insert 
> "dma-noncoherent"
> at devicetree root node.

Exactly.  ARCH_DMA_DEFAULT_COHERENTis a setting that just says for
a given architecture assumes coherent unless otherwise specified,
which has historically been the case for mips.  Not setting it means
non-coherent unless specified, which has historially been the case
for arm.

RISC-V starte out without support for non-coherent DMA, and high ups
in RISCV still told me in 2019 that RISC-V doesn't need cache
management instructions because no new hardware would ever not be
dma coherent.  Yeah, right..

Anyay, Linux for RISC-V has historically been coherent only and then
coherent default, so this option is wrong, and you need to mark
you platform as non-coherent by inserting dma-noncoherent somewhere.


  reply	other threads:[~2023-12-22  4:14 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-21 18:51 [PATCH 1/1] riscv: set ARCH_DMA_DEFAULT_COHERENT if RISCV_DMA_NONCOHERENT is not set Maxim Kochetkov
2023-12-21 18:51 ` Maxim Kochetkov
2023-12-21 20:29 ` Conor Dooley
2023-12-21 20:29   ` Conor Dooley
2023-12-21 22:27   ` Jiaxun Yang
2023-12-21 22:27     ` Jiaxun Yang
2023-12-22  4:14     ` Christoph Hellwig [this message]
2023-12-22  4:14       ` Christoph Hellwig
2023-12-22 14:39       ` Maxim Kochetkov
2023-12-22 14:39         ` Maxim Kochetkov
2023-12-22 14:54         ` Conor Dooley
2023-12-22 14:54           ` Conor Dooley
2023-12-22 15:04           ` Christoph Hellwig
2023-12-22 15:04             ` Christoph Hellwig
2023-12-22 15:38           ` Maxim Kochetkov
2023-12-22 15:38             ` Maxim Kochetkov
2023-12-22 15:45             ` Jiaxun Yang
2023-12-22 15:45               ` Jiaxun Yang
2023-12-22 15:53               ` Maxim Kochetkov
2023-12-22 15:53                 ` Maxim Kochetkov
2023-12-22 16:01                 ` Jiaxun Yang
2023-12-22 16:01                   ` Jiaxun Yang
2023-12-23  4:59                   ` Christoph Hellwig
2023-12-23  4:59                     ` Christoph Hellwig
2023-12-25  6:47                     ` Maxim Kochetkov
2023-12-25  6:47                       ` Maxim Kochetkov

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