kernel/smp.c:179:12: warning: suggest explicit braces to avoid ambiguous 'else'

kernel/smp.c:179:12: warning: suggest explicit braces to avoid ambiguous 'else'

[kernel test robot]

tree:   https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git lts/5.4.119-20.0009
head:   3bf5c3f6e32e9cfe13f09bac3ae93b8e39d472c1
commit: 505452dd073c1a8f6faa0bda630a39b375055edc smp: introduce a new interface smp_call_function_many_async
date:   2 years, 9 months ago
config: x86_64-oc_base_config (https://download.01.org/0day-ci/archive/20231230/202312301105.WG2MPikp-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231230/202312301105.WG2MPikp-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312301105.WG2MPikp-lkp@intel.com/

All warnings (new ones prefixed by >>):

   kernel/smp.c: In function 'generic_exec_single':
>> kernel/smp.c:179:12: warning: suggest explicit braces to avoid ambiguous 'else' [-Wdangling-else]
     179 |         if (llist_add(&csd->llist, &per_cpu(call_single_queue, cpu)))
         |            ^


vim +/else +179 kernel/smp.c

^590eaf1fec755 Kaixu Xia 2021-03-16  136  
^590eaf1fec755 Kaixu Xia 2021-03-16  137  /*
^590eaf1fec755 Kaixu Xia 2021-03-16  138   * Insert a previously allocated call_single_data_t element
^590eaf1fec755 Kaixu Xia 2021-03-16  139   * for execution on the given CPU. data must already have
^590eaf1fec755 Kaixu Xia 2021-03-16  140   * ->func, ->info, and ->flags set.
^590eaf1fec755 Kaixu Xia 2021-03-16  141   */
^590eaf1fec755 Kaixu Xia 2021-03-16  142  static int generic_exec_single(int cpu, call_single_data_t *csd,
505452dd073c1a yongduan  2021-03-18  143  			       smp_call_func_t func, void *info, struct cpumask *mask)
^590eaf1fec755 Kaixu Xia 2021-03-16  144  {
^590eaf1fec755 Kaixu Xia 2021-03-16  145  	if (cpu == smp_processor_id()) {
^590eaf1fec755 Kaixu Xia 2021-03-16  146  		unsigned long flags;
^590eaf1fec755 Kaixu Xia 2021-03-16  147  
^590eaf1fec755 Kaixu Xia 2021-03-16  148  		/*
^590eaf1fec755 Kaixu Xia 2021-03-16  149  		 * We can unlock early even for the synchronous on-stack case,
^590eaf1fec755 Kaixu Xia 2021-03-16  150  		 * since we're doing this from the same CPU..
^590eaf1fec755 Kaixu Xia 2021-03-16  151  		 */
^590eaf1fec755 Kaixu Xia 2021-03-16  152  		csd_unlock(csd);
^590eaf1fec755 Kaixu Xia 2021-03-16  153  		local_irq_save(flags);
^590eaf1fec755 Kaixu Xia 2021-03-16  154  		func(info);
^590eaf1fec755 Kaixu Xia 2021-03-16  155  		local_irq_restore(flags);
^590eaf1fec755 Kaixu Xia 2021-03-16  156  		return 0;
^590eaf1fec755 Kaixu Xia 2021-03-16  157  	}
^590eaf1fec755 Kaixu Xia 2021-03-16  158  
^590eaf1fec755 Kaixu Xia 2021-03-16  159  
^590eaf1fec755 Kaixu Xia 2021-03-16  160  	if ((unsigned)cpu >= nr_cpu_ids || !cpu_online(cpu)) {
^590eaf1fec755 Kaixu Xia 2021-03-16  161  		csd_unlock(csd);
^590eaf1fec755 Kaixu Xia 2021-03-16  162  		return -ENXIO;
^590eaf1fec755 Kaixu Xia 2021-03-16  163  	}
^590eaf1fec755 Kaixu Xia 2021-03-16  164  
^590eaf1fec755 Kaixu Xia 2021-03-16  165  	csd->func = func;
^590eaf1fec755 Kaixu Xia 2021-03-16  166  	csd->info = info;
^590eaf1fec755 Kaixu Xia 2021-03-16  167  
^590eaf1fec755 Kaixu Xia 2021-03-16  168  	/*
^590eaf1fec755 Kaixu Xia 2021-03-16  169  	 * The list addition should be visible before sending the IPI
^590eaf1fec755 Kaixu Xia 2021-03-16  170  	 * handler locks the list to pull the entry off it because of
^590eaf1fec755 Kaixu Xia 2021-03-16  171  	 * normal cache coherency rules implied by spinlocks.
^590eaf1fec755 Kaixu Xia 2021-03-16  172  	 *
^590eaf1fec755 Kaixu Xia 2021-03-16  173  	 * If IPIs can go out of order to the cache coherency protocol
^590eaf1fec755 Kaixu Xia 2021-03-16  174  	 * in an architecture, sufficient synchronisation should be added
^590eaf1fec755 Kaixu Xia 2021-03-16  175  	 * to arch code to make it appear to obey cache coherency WRT
^590eaf1fec755 Kaixu Xia 2021-03-16  176  	 * locking and barrier primitives. Generic code isn't really
^590eaf1fec755 Kaixu Xia 2021-03-16  177  	 * equipped to do the right thing...
^590eaf1fec755 Kaixu Xia 2021-03-16  178  	 */
^590eaf1fec755 Kaixu Xia 2021-03-16 @179  	if (llist_add(&csd->llist, &per_cpu(call_single_queue, cpu)))
505452dd073c1a yongduan  2021-03-18  180  		if (!mask) arch_send_call_function_single_ipi(cpu);
505452dd073c1a yongduan  2021-03-18  181  		else __cpumask_set_cpu(cpu, mask);
^590eaf1fec755 Kaixu Xia 2021-03-16  182  
^590eaf1fec755 Kaixu Xia 2021-03-16  183  	return 0;
^590eaf1fec755 Kaixu Xia 2021-03-16  184  }
^590eaf1fec755 Kaixu Xia 2021-03-16  185  

:::::: The code at line 179 was first introduced by commit
:::::: 590eaf1fec755215547690e787cc7d83f58ea948 Init Repo base on linux 5.4.32 long term, and add base tlinux kernel interfaces.

:::::: TO: Kaixu Xia <kaixuxia@tencent.com>
:::::: CC: Kaixu Xia <kaixuxia@tencent.com>

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki