Re: [PATCH] pwm: imx27: workaround of the pwm output bug

From: Francesco Dolcini <francesco@dolcini.it>
To: pratikmanvar09@gmail.com
Cc: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de,
	shawnguo@kernel.org, s.hauer@pengutronix.de,
	kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
	linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Clark Wang <xiaoning.wang@nxp.com>,
	Jun Li <jun.li@nxp.com>, Pratik Manvar <pratik.manvar@ifm.com>
Subject: Re: [PATCH] pwm: imx27: workaround of the pwm output bug
Date: Wed, 3 Jan 2024 11:34:21 +0100	[thread overview]
Message-ID: <20240103103421.GA3758@francesco-nb> (raw)
In-Reply-To: <20231229063013.1786-1-pratikmanvar09@gmail.com>

On Fri, Dec 29, 2023 at 12:00:07PM +0530, pratikmanvar09@gmail.com wrote:
> From: Clark Wang <xiaoning.wang@nxp.com>
> 
> This fixes the pwm output bug when decrease the duty cycle.
> This is a limited workaround for the PWM IP issue TKT0577206.
> 
> Root cause:
> When the SAR FIFO is empty, the new write value will be directly applied
> to SAR even the current period is not over.
> If the new SAR value is less than the old one, and the counter is
> greater than the new SAR value, the current period will not filp the
> level. This will result in a pulse with a duty cycle of 100%.
> 
> Workaround:
> Add an old value SAR write before updating the new duty cycle to SAR.
> This will keep the new value is always in a not empty fifo, and can be
> wait to update after a period finished.
> 
> Limitation:
> This workaround can only solve this issue when the PWM period is longer
> than 2us(or <500KHz).
> 
> Reviewed-by: Jun Li <jun.li@nxp.com>
> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
> Link: https://github.com/nxp-imx/linux-imx/commit/16181cc4eee61d87cbaba0e5a479990507816317
> Tested-by: Pratik Manvar <pratik.manvar@ifm.com>

You need to add your signed-off-by at the end when sending a patch, no
matter if you are the author or not.

Francesco