* [PATCH v2 1/4] memory: ti-gpmc: Fix build
2024-01-11 13:19 [PATCH v2 0/4] mtd: omap_gpmc: Fix GPMC & NAND drivers Roger Quadros
@ 2024-01-11 13:19 ` Roger Quadros
2024-01-12 9:45 ` Dario Binacchi
2024-01-11 13:19 ` [PATCH v2 2/4] mtd: rawnand: omap_gpmc: Use DT provided IO address Roger Quadros
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Roger Quadros @ 2024-01-11 13:19 UTC (permalink / raw)
To: trini, dario.binacchi, michael
Cc: vigneshr, nm, praneeth, afd, srk, u-boot, Roger Quadros
sys_proto.h no longer exists for K3 platform so drop it.
Include sizes.h to so SZ_16M is visible.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
Notes:
v2: no change
drivers/memory/ti-gpmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c
index 775e78c9a5..0b8674339e 100644
--- a/drivers/memory/ti-gpmc.c
+++ b/drivers/memory/ti-gpmc.c
@@ -6,7 +6,6 @@
*/
#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
#include <clk.h>
#include <common.h>
#include <dm.h>
@@ -17,6 +16,7 @@
#include <linux/mtd/omap_gpmc.h>
#include <linux/ioport.h>
#include <linux/io.h>
+#include <linux/sizes.h>
#include "ti-gpmc.h"
enum gpmc_clk_domain {
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 1/4] memory: ti-gpmc: Fix build
2024-01-11 13:19 ` [PATCH v2 1/4] memory: ti-gpmc: Fix build Roger Quadros
@ 2024-01-12 9:45 ` Dario Binacchi
0 siblings, 0 replies; 8+ messages in thread
From: Dario Binacchi @ 2024-01-12 9:45 UTC (permalink / raw)
To: Roger Quadros; +Cc: trini, michael, vigneshr, nm, praneeth, afd, srk, u-boot
Hi Roger,
On Thu, Jan 11, 2024 at 2:19 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> sys_proto.h no longer exists for K3 platform so drop it.
> Include sizes.h to so SZ_16M is visible.
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>
> Notes:
> v2: no change
>
> drivers/memory/ti-gpmc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/memory/ti-gpmc.c b/drivers/memory/ti-gpmc.c
> index 775e78c9a5..0b8674339e 100644
> --- a/drivers/memory/ti-gpmc.c
> +++ b/drivers/memory/ti-gpmc.c
> @@ -6,7 +6,6 @@
> */
>
> #include <asm/io.h>
> -#include <asm/arch/sys_proto.h>
> #include <clk.h>
> #include <common.h>
> #include <dm.h>
> @@ -17,6 +16,7 @@
> #include <linux/mtd/omap_gpmc.h>
> #include <linux/ioport.h>
> #include <linux/io.h>
> +#include <linux/sizes.h>
> #include "ti-gpmc.h"
>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Thanks and regards,
Dario
> enum gpmc_clk_domain {
> --
> 2.34.1
>
--
Dario Binacchi
Senior Embedded Linux Developer
dario.binacchi@amarulasolutions.com
__________________________________
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/4] mtd: rawnand: omap_gpmc: Use DT provided IO address
2024-01-11 13:19 [PATCH v2 0/4] mtd: omap_gpmc: Fix GPMC & NAND drivers Roger Quadros
2024-01-11 13:19 ` [PATCH v2 1/4] memory: ti-gpmc: Fix build Roger Quadros
@ 2024-01-11 13:19 ` Roger Quadros
2024-01-12 9:46 ` Dario Binacchi
2024-01-11 13:19 ` [PATCH v2 3/4] mtd: rawnand: omap_gpmc: fix OF based partition parsing for NAND Roger Quadros
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Roger Quadros @ 2024-01-11 13:19 UTC (permalink / raw)
To: trini, dario.binacchi, michael
Cc: vigneshr, nm, praneeth, afd, srk, u-boot, Roger Quadros
For DM case we can get the NAND chip's IO address from DT
so we don't need to rely on CFG_SYS_NAND_BASE.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
Notes:
v2: no change
drivers/mtd/nand/raw/omap_gpmc.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 0e25bd5dc2..f827c578d9 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -8,13 +8,15 @@
#include <log.h>
#include <system-constants.h>
#include <asm/io.h>
-#include <dm/uclass.h>
+#include <dm.h>
#include <linux/errno.h>
#ifdef CONFIG_ARCH_OMAP2PLUS
#include <asm/arch/mem.h>
#endif
+#include <linux/io.h>
+#include <linux/ioport.h>
#include <linux/mtd/omap_gpmc.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/rawnand.h>
@@ -1124,7 +1126,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
* nand_scan about special functionality. See the defines for further
* explanation
*/
-int gpmc_nand_init(struct nand_chip *nand)
+int gpmc_nand_init(struct nand_chip *nand, void __iomem *nand_base)
{
int32_t gpmc_config = 0;
int cs = cs_next++;
@@ -1164,7 +1166,7 @@ int gpmc_nand_init(struct nand_chip *nand)
info->control = NULL;
info->cs = cs;
info->ws = wscfg[cs];
- info->fifo = (void __iomem *)CFG_SYS_NAND_BASE;
+ info->fifo = nand_base;
nand_set_controller_data(nand, &omap_nand_info[cs]);
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
@@ -1214,9 +1216,16 @@ static int gpmc_nand_probe(struct udevice *dev)
{
struct nand_chip *nand = dev_get_priv(dev);
struct mtd_info *mtd = nand_to_mtd(nand);
+ struct resource res;
+ void __iomem *base;
int ret;
- gpmc_nand_init(nand);
+ ret = dev_read_resource(dev, 0, &res);
+ if (ret)
+ return ret;
+
+ base = devm_ioremap(dev, res.start, resource_size(&res));
+ gpmc_nand_init(nand, base);
ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
if (ret)
@@ -1270,7 +1279,7 @@ void board_nand_init(void)
int board_nand_init(struct nand_chip *nand)
{
- return gpmc_nand_init(nand);
+ return gpmc_nand_init(nand, (void __iomem *)CFG_SYS_NAND_BASE);
}
#endif /* CONFIG_SYS_NAND_SELF_INIT */
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/4] mtd: rawnand: omap_gpmc: Use DT provided IO address
2024-01-11 13:19 ` [PATCH v2 2/4] mtd: rawnand: omap_gpmc: Use DT provided IO address Roger Quadros
@ 2024-01-12 9:46 ` Dario Binacchi
0 siblings, 0 replies; 8+ messages in thread
From: Dario Binacchi @ 2024-01-12 9:46 UTC (permalink / raw)
To: Roger Quadros; +Cc: trini, michael, vigneshr, nm, praneeth, afd, srk, u-boot
Hi Roger,
On Thu, Jan 11, 2024 at 2:19 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> For DM case we can get the NAND chip's IO address from DT
> so we don't need to rely on CFG_SYS_NAND_BASE.
>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
>
> Notes:
> v2: no change
>
> drivers/mtd/nand/raw/omap_gpmc.c | 19 ++++++++++++++-----
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
> index 0e25bd5dc2..f827c578d9 100644
> --- a/drivers/mtd/nand/raw/omap_gpmc.c
> +++ b/drivers/mtd/nand/raw/omap_gpmc.c
> @@ -8,13 +8,15 @@
> #include <log.h>
> #include <system-constants.h>
> #include <asm/io.h>
> -#include <dm/uclass.h>
> +#include <dm.h>
> #include <linux/errno.h>
>
> #ifdef CONFIG_ARCH_OMAP2PLUS
> #include <asm/arch/mem.h>
> #endif
>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> #include <linux/mtd/omap_gpmc.h>
> #include <linux/mtd/nand_ecc.h>
> #include <linux/mtd/rawnand.h>
> @@ -1124,7 +1126,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
> * nand_scan about special functionality. See the defines for further
> * explanation
> */
> -int gpmc_nand_init(struct nand_chip *nand)
> +int gpmc_nand_init(struct nand_chip *nand, void __iomem *nand_base)
> {
> int32_t gpmc_config = 0;
> int cs = cs_next++;
> @@ -1164,7 +1166,7 @@ int gpmc_nand_init(struct nand_chip *nand)
> info->control = NULL;
> info->cs = cs;
> info->ws = wscfg[cs];
> - info->fifo = (void __iomem *)CFG_SYS_NAND_BASE;
> + info->fifo = nand_base;
> nand_set_controller_data(nand, &omap_nand_info[cs]);
> nand->cmd_ctrl = omap_nand_hwcontrol;
> nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
> @@ -1214,9 +1216,16 @@ static int gpmc_nand_probe(struct udevice *dev)
> {
> struct nand_chip *nand = dev_get_priv(dev);
> struct mtd_info *mtd = nand_to_mtd(nand);
> + struct resource res;
> + void __iomem *base;
> int ret;
>
> - gpmc_nand_init(nand);
> + ret = dev_read_resource(dev, 0, &res);
> + if (ret)
> + return ret;
> +
> + base = devm_ioremap(dev, res.start, resource_size(&res));
> + gpmc_nand_init(nand, base);
>
> ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
> if (ret)
> @@ -1270,7 +1279,7 @@ void board_nand_init(void)
>
> int board_nand_init(struct nand_chip *nand)
> {
> - return gpmc_nand_init(nand);
> + return gpmc_nand_init(nand, (void __iomem *)CFG_SYS_NAND_BASE);
> }
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Thanks and regards,
Dario
>
> #endif /* CONFIG_SYS_NAND_SELF_INIT */
> --
> 2.34.1
>
--
Dario Binacchi
Senior Embedded Linux Developer
dario.binacchi@amarulasolutions.com
__________________________________
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/4] mtd: rawnand: omap_gpmc: fix OF based partition parsing for NAND
2024-01-11 13:19 [PATCH v2 0/4] mtd: omap_gpmc: Fix GPMC & NAND drivers Roger Quadros
2024-01-11 13:19 ` [PATCH v2 1/4] memory: ti-gpmc: Fix build Roger Quadros
2024-01-11 13:19 ` [PATCH v2 2/4] mtd: rawnand: omap_gpmc: Use DT provided IO address Roger Quadros
@ 2024-01-11 13:19 ` Roger Quadros
2024-01-11 13:19 ` [PATCH v2 4/4] arm: mach-k3: am642: Define NAND boot device Roger Quadros
2024-01-15 9:42 ` [PATCH v2 0/4] mtd: omap_gpmc: Fix GPMC & NAND drivers Dario Binacchi
4 siblings, 0 replies; 8+ messages in thread
From: Roger Quadros @ 2024-01-11 13:19 UTC (permalink / raw)
To: trini, dario.binacchi, michael
Cc: vigneshr, nm, praneeth, afd, srk, u-boot, Roger Quadros
Set NAND chip ofnode and device so OF based partition parsing
can work.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
Notes:
v2: initial commit
drivers/mtd/nand/raw/omap_gpmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index f827c578d9..b36b6fabae 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -1226,6 +1226,8 @@ static int gpmc_nand_probe(struct udevice *dev)
base = devm_ioremap(dev, res.start, resource_size(&res));
gpmc_nand_init(nand, base);
+ mtd->dev = dev;
+ nand_set_flash_node(nand, dev_ofnode(dev));
ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
if (ret)
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 4/4] arm: mach-k3: am642: Define NAND boot device
2024-01-11 13:19 [PATCH v2 0/4] mtd: omap_gpmc: Fix GPMC & NAND drivers Roger Quadros
` (2 preceding siblings ...)
2024-01-11 13:19 ` [PATCH v2 3/4] mtd: rawnand: omap_gpmc: fix OF based partition parsing for NAND Roger Quadros
@ 2024-01-11 13:19 ` Roger Quadros
2024-01-15 9:42 ` [PATCH v2 0/4] mtd: omap_gpmc: Fix GPMC & NAND drivers Dario Binacchi
4 siblings, 0 replies; 8+ messages in thread
From: Roger Quadros @ 2024-01-11 13:19 UTC (permalink / raw)
To: trini, dario.binacchi, michael
Cc: vigneshr, nm, praneeth, afd, srk, u-boot, Roger Quadros
AM642 SoC supports booting from GPMC NAND device.
Define boot device for it.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
Notes:
v2: No change
arch/arm/mach-k3/am642_init.c | 3 +++
arch/arm/mach-k3/include/mach/am64_spl.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 6085379f1d..ddf47ef0a9 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -348,6 +348,9 @@ static u32 __get_primary_bootmedia(u32 main_devstat)
case BOOT_DEVICE_EMMC:
return BOOT_DEVICE_MMC1;
+ case BOOT_DEVICE_NAND:
+ return BOOT_DEVICE_NAND;
+
case BOOT_DEVICE_MMC:
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h
index b4f396b2c0..a0a517019c 100644
--- a/arch/arm/mach-k3/include/mach/am64_spl.h
+++ b/arch/arm/mach-k3/include/mach/am64_spl.h
@@ -22,6 +22,7 @@
#define BOOT_DEVICE_USB 0x2A
#define BOOT_DEVICE_DFU 0x0A
+#define BOOT_DEVICE_NAND 0x0B
#define BOOT_DEVICE_GPMC_NOR 0x0C
#define BOOT_DEVICE_PCIE 0x0D
#define BOOT_DEVICE_XSPI 0x0E
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 0/4] mtd: omap_gpmc: Fix GPMC & NAND drivers
2024-01-11 13:19 [PATCH v2 0/4] mtd: omap_gpmc: Fix GPMC & NAND drivers Roger Quadros
` (3 preceding siblings ...)
2024-01-11 13:19 ` [PATCH v2 4/4] arm: mach-k3: am642: Define NAND boot device Roger Quadros
@ 2024-01-15 9:42 ` Dario Binacchi
4 siblings, 0 replies; 8+ messages in thread
From: Dario Binacchi @ 2024-01-15 9:42 UTC (permalink / raw)
To: Roger Quadros; +Cc: trini, michael, vigneshr, nm, praneeth, afd, srk, u-boot
On Thu, Jan 11, 2024 at 2:19 PM Roger Quadros <rogerq@kernel.org> wrote:
>
> Hi,
>
> When testing the driver with K3 platform, build and functional
> issues were found in the ti-gpmc and omap_gpmc NAND driver.
> Fix those.
>
> cheers,
> -roger
>
> Changelog:
>
> v2:
> - Added "mtd: rawnand: omap_gpmc: fix OF based partition parsing for NAND".
> - Dropped defconfig patch.
>
> CI test results: https://github.com/u-boot/u-boot/pull/467
>
> v1:
> https://lore.kernel.org/all/20240109122605.51951-1-rogerq@kernel.org/
>
> Roger Quadros (4):
> memory: ti-gpmc: Fix build
> mtd: rawnand: omap_gpmc: Use DT provided IO address
> mtd: rawnand: omap_gpmc: fix OF based partition parsing for NAND
> arm: mach-k3: am642: Define NAND boot device
>
> arch/arm/mach-k3/am642_init.c | 3 +++
> arch/arm/mach-k3/include/mach/am64_spl.h | 1 +
> drivers/memory/ti-gpmc.c | 2 +-
> drivers/mtd/nand/raw/omap_gpmc.c | 21 ++++++++++++++++-----
> 4 files changed, 21 insertions(+), 6 deletions(-)
>
>
> base-commit: c2c598e87cfe56f5991730762c00733c5aa9a994
> prerequisite-patch-id: e0465f3e924302d1c4bd47f2129b4eb3bd9faead
> --
> 2.34.1
>
Applied to nand-next,
Thanks and regards,
Dario
--
Dario Binacchi
Senior Embedded Linux Developer
dario.binacchi@amarulasolutions.com
__________________________________
Amarula Solutions SRL
Via Le Canevare 30, 31100 Treviso, Veneto, IT
T. +39 042 243 5310
info@amarulasolutions.com
www.amarulasolutions.com
^ permalink raw reply [flat|nested] 8+ messages in thread