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From: Jonathan Cameron via <qemu-arm@nongnu.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: <qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>
Subject: Re: [PATCH 27/35] target/arm: Report VNCR_EL2 based faults correctly
Date: Tue, 16 Jan 2024 14:50:51 +0000	[thread overview]
Message-ID: <20240116145051.000004f7@Huawei.com> (raw)
In-Reply-To: <CAFEAcA-94-TeFw4AmTsuQaJROADaet8aWDEBXbt9H_gc1Fs6pg@mail.gmail.com>

On Tue, 16 Jan 2024 13:20:33 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:

> On Tue, 16 Jan 2024 at 13:09, Jonathan Cameron
> <Jonathan.Cameron@huawei.com> wrote:
> >
> > On Mon, 18 Dec 2023 11:32:57 +0000
> > Peter Maydell <peter.maydell@linaro.org> wrote:
> >  
> > > If FEAT_NV2 redirects a system register access to a memory offset
> > > from VNCR_EL2, that access might fault.  In this case we need to
> > > report the correct syndrome information:
> > >  * Data Abort, from same-EL
> > >  * no ISS information
> > >  * the VNCR bit (bit 13) is set
> > >
> > > and the exception must be taken to EL2.
> > >
> > > Save an appropriate syndrome template when generating code; we can
> > > then use that to:
> > >  * select the right target EL
> > >  * reconstitute a correct final syndrome for the data abort
> > >  * report the right syndrome if we take a FEAT_RME granule protection
> > >    fault on the VNCR-based write
> > >
> > > Note that because VNCR is bit 13, we must start keeping bit 13 in
> > > template syndromes, by adjusting ARM_INSN_START_WORD2_SHIFT.
> > >
> > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>  
> >
> > Hi Peter,
> >
> > I'm getting an unhelpful crash on calling init in a guest
> > running on top of an a76 emulated host with virtualization turned on.
> >
> > Run /sbin/init as init process
> > Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
> > CPU: 1 PID: 1 Comm: init Not tainted 6.7.0+ #1119
> > Hardware name: linux,dummy-virt (DT)
> > Call trace:
> >  dump_backtrace+0xa0/0x128
> >  show_stack+0x20/0x38
> >  dump_stack_lvl+0x48/0x60
> >  dump_stack+0x18/0x28
> >  panic+0x380/0x3c0
> >  do_exit+0x89c/0x9a0
> >  do_group_exit+0x3c/0xa0
> >  get_signal+0x968/0x970
> >  do_notify_resume+0x21c/0x1460
> >  el0_ia+0xa0/0xb0
> >  el0t_64_sync_handler+0xd0/0x130
> >  el0t_64_sync+0x190/0x198
> > SMP: stopping secondary CPUs
> > Kernel Offset: 0x2a8c93a00000 from 0xffff800080000000
> > PHYS_OFFSET: 0xffff82f980000000
> > CPU features: 0x0,00000001,7002014a,2101720b
> > Memory Limit: none
> > ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007 ]---
> >
> > Upstream kernel as of yesterday.  Nothing particular 'exciting' in the
> > configurations. Not attempting to use Nested virt.
> > -M virt,gic-version=3,virtualization=true
> > -cpu cortex-a76 (happens with max as well but switched to a76 for testing
> > to reduce possible sources of problems).
> >
> > Doesn't happen if single cpu in the guest, or if using gic v2 in both.
> >
> > Bisection points at this patch - so far no idea why but I've only
> > just started digging into this.  
> 
> Bisecting to this patch is a bit weird because at this point
> in the series emulation of FEAT_NV2 should be disabled and
> the code being added should never be used. You could put
> an assert(0) into the code in translate-a64.c before the
> call to syn_data_abort_vncr() and in arm_deliver_fault()
> assert(!is_vncr) to confirm that we're not somehow getting
> into this code for some non-FEAT_NV2 situation, I guess.

Not that, but surprisingly is_vncr == true.
in arm_deliver_fault()

Frigging that to be false gets me up and running. I'll see
if I can figure out why it is set.

J
> 
> thanks
> -- PMM


WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: <qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>
Subject: Re: [PATCH 27/35] target/arm: Report VNCR_EL2 based faults correctly
Date: Tue, 16 Jan 2024 14:50:51 +0000	[thread overview]
Message-ID: <20240116145051.000004f7@Huawei.com> (raw)
In-Reply-To: <CAFEAcA-94-TeFw4AmTsuQaJROADaet8aWDEBXbt9H_gc1Fs6pg@mail.gmail.com>

On Tue, 16 Jan 2024 13:20:33 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:

> On Tue, 16 Jan 2024 at 13:09, Jonathan Cameron
> <Jonathan.Cameron@huawei.com> wrote:
> >
> > On Mon, 18 Dec 2023 11:32:57 +0000
> > Peter Maydell <peter.maydell@linaro.org> wrote:
> >  
> > > If FEAT_NV2 redirects a system register access to a memory offset
> > > from VNCR_EL2, that access might fault.  In this case we need to
> > > report the correct syndrome information:
> > >  * Data Abort, from same-EL
> > >  * no ISS information
> > >  * the VNCR bit (bit 13) is set
> > >
> > > and the exception must be taken to EL2.
> > >
> > > Save an appropriate syndrome template when generating code; we can
> > > then use that to:
> > >  * select the right target EL
> > >  * reconstitute a correct final syndrome for the data abort
> > >  * report the right syndrome if we take a FEAT_RME granule protection
> > >    fault on the VNCR-based write
> > >
> > > Note that because VNCR is bit 13, we must start keeping bit 13 in
> > > template syndromes, by adjusting ARM_INSN_START_WORD2_SHIFT.
> > >
> > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>  
> >
> > Hi Peter,
> >
> > I'm getting an unhelpful crash on calling init in a guest
> > running on top of an a76 emulated host with virtualization turned on.
> >
> > Run /sbin/init as init process
> > Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007
> > CPU: 1 PID: 1 Comm: init Not tainted 6.7.0+ #1119
> > Hardware name: linux,dummy-virt (DT)
> > Call trace:
> >  dump_backtrace+0xa0/0x128
> >  show_stack+0x20/0x38
> >  dump_stack_lvl+0x48/0x60
> >  dump_stack+0x18/0x28
> >  panic+0x380/0x3c0
> >  do_exit+0x89c/0x9a0
> >  do_group_exit+0x3c/0xa0
> >  get_signal+0x968/0x970
> >  do_notify_resume+0x21c/0x1460
> >  el0_ia+0xa0/0xb0
> >  el0t_64_sync_handler+0xd0/0x130
> >  el0t_64_sync+0x190/0x198
> > SMP: stopping secondary CPUs
> > Kernel Offset: 0x2a8c93a00000 from 0xffff800080000000
> > PHYS_OFFSET: 0xffff82f980000000
> > CPU features: 0x0,00000001,7002014a,2101720b
> > Memory Limit: none
> > ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007 ]---
> >
> > Upstream kernel as of yesterday.  Nothing particular 'exciting' in the
> > configurations. Not attempting to use Nested virt.
> > -M virt,gic-version=3,virtualization=true
> > -cpu cortex-a76 (happens with max as well but switched to a76 for testing
> > to reduce possible sources of problems).
> >
> > Doesn't happen if single cpu in the guest, or if using gic v2 in both.
> >
> > Bisection points at this patch - so far no idea why but I've only
> > just started digging into this.  
> 
> Bisecting to this patch is a bit weird because at this point
> in the series emulation of FEAT_NV2 should be disabled and
> the code being added should never be used. You could put
> an assert(0) into the code in translate-a64.c before the
> call to syn_data_abort_vncr() and in arm_deliver_fault()
> assert(!is_vncr) to confirm that we're not somehow getting
> into this code for some non-FEAT_NV2 situation, I guess.

Not that, but surprisingly is_vncr == true.
in arm_deliver_fault()

Frigging that to be false gets me up and running. I'll see
if I can figure out why it is set.

J
> 
> thanks
> -- PMM



  reply	other threads:[~2024-01-16 14:51 UTC|newest]

Thread overview: 87+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-18 11:32 [PATCH 00/35] target/arm: Implement emulation of nested virtualization Peter Maydell
2023-12-18 11:32 ` [PATCH 01/35] target/arm: Don't implement *32_EL2 registers when EL1 is AArch64 only Peter Maydell
2023-12-18 11:32 ` [PATCH 02/35] target/arm: Set CTR_EL0.{IDC,DIC} for the 'max' CPU Peter Maydell
2023-12-27 21:08   ` [PATCH 02/35] target/arm: Set CTR_EL0.{IDC, DIC} " Richard Henderson
2023-12-18 11:32 ` [PATCH 03/35] hw/intc/arm_gicv3_cpuif: handle LPIs in in the list registers Peter Maydell
2023-12-27 21:11   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 04/35] target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NV Peter Maydell
2023-12-27 21:42   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 05/35] target/arm: Implement HCR_EL2.AT handling Peter Maydell
2023-12-27 22:01   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 06/35] target/arm: Enable trapping of ERET for FEAT_NV Peter Maydell
2023-12-27 22:06   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 07/35] target/arm: Always honour HCR_EL2.TSC when HCR_EL2.NV is set Peter Maydell
2023-12-27 22:18   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 08/35] target/arm: Allow use of upper 32 bits of TBFLAG_A64 Peter Maydell
2023-12-27 22:20   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 09/35] target/arm: Record correct opcode fields in cpreg for E2H aliases Peter Maydell
2023-12-27 22:23   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 10/35] target/arm: *_EL12 registers should UNDEF when HCR_EL2.E2H is 0 Peter Maydell
2023-12-27 22:25   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 11/35] target/arm: Make EL2 cpreg accessfns safe for FEAT_NV EL1 accesses Peter Maydell
2023-12-27 22:31   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 12/35] target/arm: Move FPU/SVE/SME access checks up above ARM_CP_SPECIAL_MASK check Peter Maydell
2023-12-27 22:32   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 13/35] target/arm: Trap sysreg accesses for FEAT_NV Peter Maydell
2023-12-27 22:40   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 14/35] target/arm: Make NV reads of CurrentEL return EL2 Peter Maydell
2023-12-27 22:42   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 15/35] target/arm: Set SPSR_EL1.M correctly when nested virt is enabled Peter Maydell
2023-12-27 22:43   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 16/35] target/arm: Trap registers when HCR_EL2.{NV, NV1} == {1, 1} Peter Maydell
2023-12-27 22:47   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 17/35] target/arm: Always use arm_pan_enabled() when checking if PAN is enabled Peter Maydell
2023-12-27 22:50   ` Richard Henderson
2024-01-04 15:59     ` Peter Maydell
2023-12-18 11:32 ` [PATCH 18/35] target/arm: Don't honour PSTATE.PAN when HCR_EL2.{NV, NV1} == {1, 1} Peter Maydell
2023-12-27 22:52   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 19/35] target/arm: Treat LDTR* and STTR* as LDR/STR when NV, NV1 is 1, 1 Peter Maydell
2023-12-27 22:53   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 20/35] target/arm: Handle FEAT_NV page table attribute changes Peter Maydell
2023-12-27 22:57   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 21/35] target/arm: Add FEAT_NV to max, neoverse-n2, neoverse-v1 CPUs Peter Maydell
2023-12-27 22:59   ` Richard Henderson
2023-12-29 11:37   ` Marcin Juszkiewicz
2024-01-04 11:36     ` Peter Maydell
2023-12-18 11:32 ` [PATCH 22/35] target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits Peter Maydell
2023-12-27 22:59   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 23/35] target/arm: Implement VNCR_EL2 register Peter Maydell
2023-12-27 23:01   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 24/35] target/arm: Handle FEAT_NV2 changes to when SPSR_EL1.M reports EL2 Peter Maydell
2023-12-27 23:06   ` Richard Henderson
2024-01-04 16:03     ` Peter Maydell
2023-12-18 11:32 ` [PATCH 25/35] target/arm: Handle FEAT_NV2 redirection of SPSR_EL2, ELR_EL2, ESR_EL2, FAR_EL2 Peter Maydell
2023-12-27 23:11   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 26/35] target/arm: Implement FEAT_NV2 redirection of sysregs to RAM Peter Maydell
2023-12-27 23:55   ` Richard Henderson
2024-01-04 16:23     ` Peter Maydell
2024-01-09  8:40       ` Richard Henderson
2023-12-18 11:32 ` [PATCH 27/35] target/arm: Report VNCR_EL2 based faults correctly Peter Maydell
2023-12-28  0:03   ` Richard Henderson
2024-01-16 13:09   ` Jonathan Cameron via
2024-01-16 13:09     ` Jonathan Cameron via
2024-01-16 13:20     ` Peter Maydell
2024-01-16 14:50       ` Jonathan Cameron via [this message]
2024-01-16 14:50         ` Jonathan Cameron via
2024-01-16 14:59         ` Peter Maydell
2024-01-16 15:29           ` Jonathan Cameron via
2024-01-16 15:29             ` Jonathan Cameron via
2024-01-16 15:35             ` Peter Maydell
2023-12-18 11:32 ` [PATCH 28/35] target/arm: Mark up VNCR offsets (offsets 0x0..0xff) Peter Maydell
2023-12-28  0:35   ` Richard Henderson
2023-12-18 11:32 ` [PATCH 29/35] target/arm: Mark up VNCR offsets (offsets 0x100..0x160) Peter Maydell
2023-12-28  0:42   ` Richard Henderson
2024-01-04 16:24     ` Peter Maydell
2023-12-18 11:33 ` [PATCH 30/35] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8) Peter Maydell
2023-12-28  0:45   ` Richard Henderson
2023-12-18 11:33 ` [PATCH 31/35] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) Peter Maydell
2023-12-28  0:50   ` Richard Henderson
2023-12-18 11:33 ` [PATCH 32/35] hw/intc/arm_gicv3_cpuif: Mark up VNCR offsets for GIC CPU registers Peter Maydell
2023-12-28  0:52   ` Richard Henderson
2023-12-18 11:33 ` [PATCH 33/35] target/arm: Report HCR_EL2.{NV,NV1,NV2} in cpu dumps Peter Maydell
2023-12-28  0:54   ` Richard Henderson
2023-12-18 11:33 ` [PATCH 34/35] target/arm: Enhance CPU_LOG_INT to show SPSR on AArch64 exception-entry Peter Maydell
2023-12-28  0:54   ` Richard Henderson
2023-12-18 11:33 ` [PATCH 35/35] target/arm: Add FEAT_NV2 to max, neoverse-n2, neoverse-v1 CPUs Peter Maydell
2023-12-28  0:58   ` Richard Henderson
2023-12-22 14:23 ` [PATCH 00/35] target/arm: Implement emulation of nested virtualization Miguel Luis

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