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From: Conor Dooley <conor@kernel.org>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	linux-kernel@vger.kernel.org, Alexandre Ghiti <alex@ghiti.fr>,
	linux-riscv@lists.infradead.org,
	Stefan O'Rear <sorear@fastmail.com>,
	stable@vger.kernel.org
Subject: Re: [PATCH -fixes v4 1/3] riscv: Fix enabling cbo.zero when running in M-mode
Date: Wed, 28 Feb 2024 10:13:52 +0000	[thread overview]
Message-ID: <20240228-rarity-underuse-4ea0ceaa9688@spud> (raw)
In-Reply-To: <20240228065559.3434837-2-samuel.holland@sifive.com>


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On Tue, Feb 27, 2024 at 10:55:33PM -0800, Samuel Holland wrote:
> When the kernel is running in M-mode, the CBZE bit must be set in the
> menvcfg CSR, not in senvcfg.
> 
> Cc: <stable@vger.kernel.org>
> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode")
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	linux-kernel@vger.kernel.org, Alexandre Ghiti <alex@ghiti.fr>,
	linux-riscv@lists.infradead.org,
	Stefan O'Rear <sorear@fastmail.com>,
	stable@vger.kernel.org
Subject: Re: [PATCH -fixes v4 1/3] riscv: Fix enabling cbo.zero when running in M-mode
Date: Wed, 28 Feb 2024 10:13:52 +0000	[thread overview]
Message-ID: <20240228-rarity-underuse-4ea0ceaa9688@spud> (raw)
In-Reply-To: <20240228065559.3434837-2-samuel.holland@sifive.com>

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On Tue, Feb 27, 2024 at 10:55:33PM -0800, Samuel Holland wrote:
> When the kernel is running in M-mode, the CBZE bit must be set in the
> menvcfg CSR, not in senvcfg.
> 
> Cc: <stable@vger.kernel.org>
> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode")
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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  reply	other threads:[~2024-02-28 10:14 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-28  6:55 [PATCH -fixes v4 0/3] riscv: cbo.zero fixes Samuel Holland
2024-02-28  6:55 ` Samuel Holland
2024-02-28  6:55 ` [PATCH -fixes v4 1/3] riscv: Fix enabling cbo.zero when running in M-mode Samuel Holland
2024-02-28  6:55   ` Samuel Holland
2024-02-28 10:13   ` Conor Dooley [this message]
2024-02-28 10:13     ` Conor Dooley
2024-02-28  6:55 ` [PATCH -fixes v4 2/3] riscv: Add a custom ISA extension for the [ms]envcfg CSR Samuel Holland
2024-02-28  6:55   ` Samuel Holland
2024-02-28 10:12   ` Conor Dooley
2024-02-28 10:12     ` Conor Dooley
2024-02-29 18:23     ` Palmer Dabbelt
2024-02-29 18:23       ` Palmer Dabbelt
2024-02-29 18:30       ` Conor Dooley
2024-02-29 18:30         ` Conor Dooley
2024-02-29 23:40         ` Palmer Dabbelt
2024-02-29 23:40           ` Palmer Dabbelt
2024-02-28 13:23   ` Andrew Jones
2024-02-28 13:23     ` Andrew Jones
2024-02-28  6:55 ` [PATCH -fixes v4 3/3] riscv: Save/restore envcfg CSR during CPU suspend Samuel Holland
2024-02-28  6:55   ` Samuel Holland
2024-02-28 10:14   ` Conor Dooley
2024-02-28 10:14     ` Conor Dooley
2024-02-28 13:27   ` Andrew Jones
2024-02-28 13:27     ` Andrew Jones
2024-02-29 22:10 ` [PATCH -fixes v4 0/3] riscv: cbo.zero fixes patchwork-bot+linux-riscv
2024-02-29 22:10   ` patchwork-bot+linux-riscv

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