[QEMU PATCH v6 0/1] S3 support

[QEMU PATCH v6 0/1] S3 support

[Jiqian Chen]

Hi all,
This is the v6 patch to support S3.
In current code, when guest does S3, virtio devices are reset during that
process, that causes the display resources of virtio-gpu are destroyed,
then the display can't come back after resuming.
This v6 patch implement the No_Soft_Reset bit of PCI_PM_CTRL register,
when this bit is set, the resetting will not be done, so that the display
can work after resuming.
This version abandons all previous version implementations and is a new
different solution according to the outcome of the discussion and
suggestions in the mailing thread of virtio-spec.
(https://lists.oasis-open.org/archives/virtio-comment/202401/msg00077.html)

Best regards,
Jiqian Chen

V5:
Hi all,
v5 makes below changes:
* Since this series patches add a new mechanism that let virtgpu and Qemu can negotiate
  their reset behavior, and other guys hope me can improve this mechanism to virtio pci
  level, so that other virtio devices can also benefit from it. So instead of adding
  new feature flag VIRTIO_GPU_F_FREEZE_S3 only serves for virtgpu, v5 add a new parameter
  named freeze_mode to struct VirtIODevice, when guest begin suspending, set freeze_mode
  to VIRTIO_PCI_FREEZE_MODE_FREEZE_S3, and then all virtio devices can get this status,
  and notice that guest is suspending, then they can change their reset behavior . See
  the new commit "virtio-pci: Add freeze_mode case for virtio pci"
* The second commit is just for virtgpu, when freeze_mode is VIRTIO_PCI_FREEZE_MODE_FREEZE_S3,
  prevent Qemu destroying render resources, so that the display can come back after resuming.

V5 of kernel patch:
https://lore.kernel.org/lkml/20230919104607.2282248-1-Jiqian.Chen@amd.com/T/#t

The link to trace this issue:
https://gitlab.com/qemu-project/qemu/-/issues/1860

v4:
Hi all,
Thanks for Gerd Hoffmann's advice. V4 makes below changes:
* Use enum for freeze mode, so this can be extended with more
  modes in the future.
* Rename functions and paratemers with "_S3" postfix.
And no functional changes.
Link:
https://lore.kernel.org/qemu-devel/20230720120816.8751-1-Jiqian.Chen@amd.com/
No v4 patch on kernel side.


v3:
Hi all,
Thanks for Michael S. Tsirkin's advice. V3 makes below changes:
* Remove changes in file include/standard-headers/linux/virtio_gpu.h
  I am not supposed to edit this file and it will be imported after
  the patches of linux kernel was merged.
Link:
https://lore.kernel.org/qemu-devel/20230719074726.1613088-1-Jiqian.Chen@amd.com/T/#t
V3 of kernel patch:
https://lore.kernel.org/lkml/20230720115805.8206-1-Jiqian.Chen@amd.com/T/#t


v2:
makes below changes:
* Change VIRTIO_CPU_CMD_STATUS_FREEZING to 0x0400 (<0x1000)
* Add virtio_gpu_device_unrealize to destroy resources to solve
  potential memory leak problem. This also needs hot-plug support.
* Add a new feature flag VIRTIO_GPU_F_FREEZING, so that guest and
  host can negotiate whenever freezing is supported or not.
Link:
https://lore.kernel.org/qemu-devel/20230630070016.841459-1-Jiqian.Chen@amd.com/T/#t
V2 of kernel patch:
https://lore.kernel.org/lkml/20230630073448.842767-1-Jiqian.Chen@amd.com/T/#t


v1:
Hi all,
I am working to implement virtgpu S3 function on Xen.

Currently on Xen, if we start a guest who enables virtgpu, and then run "echo mem > /sys/power/state" to suspend guest. And run "sudo xl trigger <guest id> s3resume" to resume guest. We can find that the guest kernel comes back, but the display doesn't.
It just shown a black screen.

Through reading codes, I founded that when guest was during suspending, it called into Qemu to call virtio_gpu_gl_reset. In virtio_gpu_gl_reset, it destroyed all resources and reset renderer. This made the display gone after guest resumed.

I think we should keep resources or prevent they being destroyed when guest is suspending. So, I add a new status named freezing to virtgpu, and add a new ctrl message VIRTIO_GPU_CMD_STATUS_FREEZING to get notification from guest. If freezing is set to true, and then Qemu will realize that guest is suspending, it will not destroy resources and will not reset renderer. If freezing is set to false, Qemu will do its origin actions, and has no other impaction.

And now, display can come back and applications can continue their status after guest resumes.
Link:
https://lore.kernel.org/qemu-devel/20230608025655.1674357-1-Jiqian.Chen@amd.com/
V1 of kernel patch:
https://lore.kernel.org/lkml/20230608063857.1677973-1-Jiqian.Chen@amd.com/


Jiqian Chen (1):
  virtio-pci: implement No_Soft_Reset bit

 hw/virtio/virtio-pci.c         | 37 +++++++++++++++++++++++++++++++++-
 include/hw/virtio/virtio-pci.h |  5 +++++
 2 files changed, 41 insertions(+), 1 deletion(-)

-- 
2.34.1

[QEMU PATCH v6 1/1] virtio-pci: implement No_Soft_Reset bit

[Jiqian Chen]

In current code, when guest does S3, virtio devices are reset due to
the bit No_Soft_Reset is not set. After resetting, the display resources
of virtio-gpu are destroyed, then the display can't come back and only
show blank after resuming.

Implement No_Soft_Reset bit of PCI_PM_CTRL register, then guest can check
this bit, if this bit is set, the devices resetting will not be done, and
then the display can work after resuming.

Signed-off-by: Jiqian Chen <Jiqian.Chen@amd.com>
---
 hw/virtio/virtio-pci.c         | 37 +++++++++++++++++++++++++++++++++-
 include/hw/virtio/virtio-pci.h |  5 +++++
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 1a7039fb0c68..da5312010345 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -2197,6 +2197,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
             pcie_cap_lnkctl_init(pci_dev);
         }
 
+        if (proxy->flags & VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET) {
+            pci_set_word(pci_dev->config + pos + PCI_PM_CTRL,
+                         PCI_PM_CTRL_NO_SOFT_RESET);
+        }
+
         if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
             /* Init Power Management Control Register */
             pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
@@ -2259,18 +2264,46 @@ static void virtio_pci_reset(DeviceState *qdev)
     }
 }
 
+static bool device_no_need_reset(PCIDevice *dev)
+{
+    if (pci_is_express(dev)) {
+        uint16_t pmcsr;
+
+        pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL);
+        /*
+         * When No_Soft_Reset bit is set and device
+         * is in D3hot state, can't reset device
+         */
+        if ((pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) &&
+            (pmcsr & PCI_PM_CTRL_STATE_MASK) == 3)
+            return true;
+    }
+
+    return false;
+}
+
 static void virtio_pci_bus_reset_hold(Object *obj)
 {
     PCIDevice *dev = PCI_DEVICE(obj);
     DeviceState *qdev = DEVICE(obj);
 
+    if (device_no_need_reset(dev))
+        return;
+
     virtio_pci_reset(qdev);
 
     if (pci_is_express(dev)) {
+        uint16_t pmcsr;
+        uint16_t val = 0;
+
         pcie_cap_deverr_reset(dev);
         pcie_cap_lnkctl_reset(dev);
 
-        pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
+        /* don't reset the RO bits */
+        pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL);
+        val = val | (pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) |
+                (pmcsr & PCI_PM_CTRL_DATA_SCALE_MASK);
+        pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, val);
     }
 }
 
@@ -2297,6 +2330,8 @@ static Property virtio_pci_properties[] = {
                     VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
     DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
                     VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
+    DEFINE_PROP_BIT("x-pcie-pm-no-soft-reset", VirtIOPCIProxy, flags,
+                    VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, true),
     DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
                     VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
     DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h
index 59d88018c16a..9e67ba38c748 100644
--- a/include/hw/virtio/virtio-pci.h
+++ b/include/hw/virtio/virtio-pci.h
@@ -43,6 +43,7 @@ enum {
     VIRTIO_PCI_FLAG_INIT_FLR_BIT,
     VIRTIO_PCI_FLAG_AER_BIT,
     VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT,
+    VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT,
 };
 
 /* Need to activate work-arounds for buggy guests at vmstate load. */
@@ -79,6 +80,10 @@ enum {
 /* Init Power Management */
 #define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT)
 
+/* Init The No_Soft_Reset bit of Power Management */
+#define VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET \
+  (1 << VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT)
+
 /* Init Function Level Reset capability */
 #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
 
-- 
2.34.1

Re: [QEMU PATCH v6 1/1] virtio-pci: implement No_Soft_Reset bit

[Chen, Jiqian]

Hi Michael S. Tsirkin,
Do you have any comments on this patch?

On 2024/2/22 11:40, Jiqian Chen wrote:
> In current code, when guest does S3, virtio devices are reset due to
> the bit No_Soft_Reset is not set. After resetting, the display resources
> of virtio-gpu are destroyed, then the display can't come back and only
> show blank after resuming.
> 
> Implement No_Soft_Reset bit of PCI_PM_CTRL register, then guest can check
> this bit, if this bit is set, the devices resetting will not be done, and
> then the display can work after resuming.
> 
> Signed-off-by: Jiqian Chen <Jiqian.Chen@amd.com>
> ---
>  hw/virtio/virtio-pci.c         | 37 +++++++++++++++++++++++++++++++++-
>  include/hw/virtio/virtio-pci.h |  5 +++++
>  2 files changed, 41 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
> index 1a7039fb0c68..da5312010345 100644
> --- a/hw/virtio/virtio-pci.c
> +++ b/hw/virtio/virtio-pci.c
> @@ -2197,6 +2197,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
>              pcie_cap_lnkctl_init(pci_dev);
>          }
>  
> +        if (proxy->flags & VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET) {
> +            pci_set_word(pci_dev->config + pos + PCI_PM_CTRL,
> +                         PCI_PM_CTRL_NO_SOFT_RESET);
> +        }
> +
>          if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
>              /* Init Power Management Control Register */
>              pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
> @@ -2259,18 +2264,46 @@ static void virtio_pci_reset(DeviceState *qdev)
>      }
>  }
>  
> +static bool device_no_need_reset(PCIDevice *dev)
> +{
> +    if (pci_is_express(dev)) {
> +        uint16_t pmcsr;
> +
> +        pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL);
> +        /*
> +         * When No_Soft_Reset bit is set and device
> +         * is in D3hot state, can't reset device
> +         */
> +        if ((pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) &&
> +            (pmcsr & PCI_PM_CTRL_STATE_MASK) == 3)
> +            return true;
> +    }
> +
> +    return false;
> +}
> +
>  static void virtio_pci_bus_reset_hold(Object *obj)
>  {
>      PCIDevice *dev = PCI_DEVICE(obj);
>      DeviceState *qdev = DEVICE(obj);
>  
> +    if (device_no_need_reset(dev))
> +        return;
> +
>      virtio_pci_reset(qdev);
>  
>      if (pci_is_express(dev)) {
> +        uint16_t pmcsr;
> +        uint16_t val = 0;
> +
>          pcie_cap_deverr_reset(dev);
>          pcie_cap_lnkctl_reset(dev);
>  
> -        pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
> +        /* don't reset the RO bits */
> +        pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL);
> +        val = val | (pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) |
> +                (pmcsr & PCI_PM_CTRL_DATA_SCALE_MASK);
> +        pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, val);
>      }
>  }
>  
> @@ -2297,6 +2330,8 @@ static Property virtio_pci_properties[] = {
>                      VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
>      DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
>                      VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
> +    DEFINE_PROP_BIT("x-pcie-pm-no-soft-reset", VirtIOPCIProxy, flags,
> +                    VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, true),
>      DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
>                      VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
>      DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
> diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h
> index 59d88018c16a..9e67ba38c748 100644
> --- a/include/hw/virtio/virtio-pci.h
> +++ b/include/hw/virtio/virtio-pci.h
> @@ -43,6 +43,7 @@ enum {
>      VIRTIO_PCI_FLAG_INIT_FLR_BIT,
>      VIRTIO_PCI_FLAG_AER_BIT,
>      VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT,
> +    VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT,
>  };
>  
>  /* Need to activate work-arounds for buggy guests at vmstate load. */
> @@ -79,6 +80,10 @@ enum {
>  /* Init Power Management */
>  #define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT)
>  
> +/* Init The No_Soft_Reset bit of Power Management */
> +#define VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET \
> +  (1 << VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT)
> +
>  /* Init Function Level Reset capability */
>  #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
>  

-- 
Best regards,
Jiqian Chen.

Re: [QEMU PATCH v6 1/1] virtio-pci: implement No_Soft_Reset bit

[Michael S. Tsirkin]

On Thu, Feb 22, 2024 at 11:40:10AM +0800, Jiqian Chen wrote:
> In current code, when guest does S3, virtio devices are reset due to
> the bit No_Soft_Reset is not set. After resetting, the display resources
> of virtio-gpu are destroyed, then the display can't come back and only
> show blank after resuming.
> 
> Implement No_Soft_Reset bit of PCI_PM_CTRL register, then guest can check
> this bit, if this bit is set, the devices resetting will not be done, and
> then the display can work after resuming.
> 
> Signed-off-by: Jiqian Chen <Jiqian.Chen@amd.com>
> ---
>  hw/virtio/virtio-pci.c         | 37 +++++++++++++++++++++++++++++++++-
>  include/hw/virtio/virtio-pci.h |  5 +++++
>  2 files changed, 41 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
> index 1a7039fb0c68..da5312010345 100644
> --- a/hw/virtio/virtio-pci.c
> +++ b/hw/virtio/virtio-pci.c
> @@ -2197,6 +2197,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
>              pcie_cap_lnkctl_init(pci_dev);
>          }
>  
> +        if (proxy->flags & VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET) {
> +            pci_set_word(pci_dev->config + pos + PCI_PM_CTRL,
> +                         PCI_PM_CTRL_NO_SOFT_RESET);
> +        }
> +
>          if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
>              /* Init Power Management Control Register */
>              pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,


Don't we need compat machinery to avoid breaking migration for
existing machine types?

> @@ -2259,18 +2264,46 @@ static void virtio_pci_reset(DeviceState *qdev)
>      }
>  }
>  
> +static bool device_no_need_reset(PCIDevice *dev)
> +{
> +    if (pci_is_express(dev)) {
> +        uint16_t pmcsr;
> +
> +        pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL);
> +        /*
> +         * When No_Soft_Reset bit is set and device

the device

> +         * is in D3hot state, can't reset device

can't? or don't?

> +         */
> +        if ((pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) &&
> +            (pmcsr & PCI_PM_CTRL_STATE_MASK) == 3)
> +            return true;

coding style violation

> +    }
> +
> +    return false;
> +}
> +
>  static void virtio_pci_bus_reset_hold(Object *obj)
>  {
>      PCIDevice *dev = PCI_DEVICE(obj);
>      DeviceState *qdev = DEVICE(obj);
>  
> +    if (device_no_need_reset(dev))
> +        return;
> +
>      virtio_pci_reset(qdev);
>  
>      if (pci_is_express(dev)) {
> +        uint16_t pmcsr;
> +        uint16_t val = 0;
> +
>          pcie_cap_deverr_reset(dev);
>          pcie_cap_lnkctl_reset(dev);
>  
> -        pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
> +        /* don't reset the RO bits */
> +        pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL);
> +        val = val | (pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) |
> +                (pmcsr & PCI_PM_CTRL_DATA_SCALE_MASK);
> +        pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, val);

First, we have test and clear for this.

Second, this has to be conditional on the flag, no?
Without the flag don't we reset everything?
Or you can reuse wmask for this, also an option.

Also what's going on with PCI_PM_CTRL_DATA_SCALE_MASK?
Where does that come from?

>      }
>  }
>  
> @@ -2297,6 +2330,8 @@ static Property virtio_pci_properties[] = {
>                      VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
>      DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
>                      VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
> +    DEFINE_PROP_BIT("x-pcie-pm-no-soft-reset", VirtIOPCIProxy, flags,
> +                    VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, true),
>      DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
>                      VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
>      DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
> diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h
> index 59d88018c16a..9e67ba38c748 100644
> --- a/include/hw/virtio/virtio-pci.h
> +++ b/include/hw/virtio/virtio-pci.h
> @@ -43,6 +43,7 @@ enum {
>      VIRTIO_PCI_FLAG_INIT_FLR_BIT,
>      VIRTIO_PCI_FLAG_AER_BIT,
>      VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT,
> +    VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT,
>  };
>  
>  /* Need to activate work-arounds for buggy guests at vmstate load. */
> @@ -79,6 +80,10 @@ enum {
>  /* Init Power Management */
>  #define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT)
>  
> +/* Init The No_Soft_Reset bit of Power Management */
> +#define VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET \
> +  (1 << VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT)
> +
>  /* Init Function Level Reset capability */
>  #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
>  
> -- 
> 2.34.1

Re: [QEMU PATCH v6 1/1] virtio-pci: implement No_Soft_Reset bit

[Chen, Jiqian]

On 2024/3/18 16:04, Michael S. Tsirkin wrote:
> On Thu, Feb 22, 2024 at 11:40:10AM +0800, Jiqian Chen wrote:
>> In current code, when guest does S3, virtio devices are reset due to
>> the bit No_Soft_Reset is not set. After resetting, the display resources
>> of virtio-gpu are destroyed, then the display can't come back and only
>> show blank after resuming.
>>
>> Implement No_Soft_Reset bit of PCI_PM_CTRL register, then guest can check
>> this bit, if this bit is set, the devices resetting will not be done, and
>> then the display can work after resuming.
>>
>> Signed-off-by: Jiqian Chen <Jiqian.Chen@amd.com>
>> ---
>>  hw/virtio/virtio-pci.c         | 37 +++++++++++++++++++++++++++++++++-
>>  include/hw/virtio/virtio-pci.h |  5 +++++
>>  2 files changed, 41 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
>> index 1a7039fb0c68..da5312010345 100644
>> --- a/hw/virtio/virtio-pci.c
>> +++ b/hw/virtio/virtio-pci.c
>> @@ -2197,6 +2197,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
>>              pcie_cap_lnkctl_init(pci_dev);
>>          }
>>  
>> +        if (proxy->flags & VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET) {
>> +            pci_set_word(pci_dev->config + pos + PCI_PM_CTRL,
>> +                         PCI_PM_CTRL_NO_SOFT_RESET);
>> +        }
>> +
>>          if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
>>              /* Init Power Management Control Register */
>>              pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
> 
> 
> Don't we need compat machinery to avoid breaking migration for
> existing machine types?
Could you elaborate on it? I am sorry I don't know which machine types to be compatible with, and how to be compatible with them.
Can I simply set the default value of x-pcie-pm-no-soft-reset to false? If someone need this bit, they can set x-pcie-pm-no-soft-reset=true in the config parameters for Qemu. So that will not affect exiting machine types?

> 
>> @@ -2259,18 +2264,46 @@ static void virtio_pci_reset(DeviceState *qdev)
>>      }
>>  }
>>  
>> +static bool device_no_need_reset(PCIDevice *dev)
>> +{
>> +    if (pci_is_express(dev)) {
>> +        uint16_t pmcsr;
>> +
>> +        pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL);
>> +        /*
>> +         * When No_Soft_Reset bit is set and device
> 
> the device
Will change in next version.
> 
>> +         * is in D3hot state, can't reset device
> 
> can't? or don't?
Will change to "don't" in next version.

> 
>> +         */
>> +        if ((pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) &&
>> +            (pmcsr & PCI_PM_CTRL_STATE_MASK) == 3)
>> +            return true;
> 
> coding style violation
Will add braces {} in next version.

> 
>> +    }
>> +
>> +    return false;
>> +}
>> +
>>  static void virtio_pci_bus_reset_hold(Object *obj)
>>  {
>>      PCIDevice *dev = PCI_DEVICE(obj);
>>      DeviceState *qdev = DEVICE(obj);
>>  
>> +    if (device_no_need_reset(dev))
>> +        return;
>> +
>>      virtio_pci_reset(qdev);
>>  
>>      if (pci_is_express(dev)) {
>> +        uint16_t pmcsr;
>> +        uint16_t val = 0;
>> +
>>          pcie_cap_deverr_reset(dev);
>>          pcie_cap_lnkctl_reset(dev);
>>  
>> -        pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, 0);
>> +        /* don't reset the RO bits */
>> +        pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL);
>> +        val = val | (pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) |
>> +                (pmcsr & PCI_PM_CTRL_DATA_SCALE_MASK);
>> +        pci_set_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL, val);
> 
> First, we have test and clear for this.
> 
> Second, this has to be conditional on the flag, no?
Before resetting, I first read the value of config, its function is equivalent to checking the label, right?
If the flag is set, the value of No_Soft_Reset is 1, the bit of "val" is also 1.
If the flag is not set, the value of No_Soft_Reset is 0, "val" is also 0.

> Without the flag don't we reset everything?
We need reset everything include the RO bit, right?
If so, that is my fault, then I will change to check the flag of proxy in next version.

> Or you can reuse wmask for this, also an option.
> 
> Also what's going on with PCI_PM_CTRL_DATA_SCALE_MASK?
> Where does that come from?
I read from PCI spec, the bit DATA_SCALE and No_Soft_Reset are both RO bit, so I thought we shouldn't reset them.
It is something wrong with my understanding, I will remove PCI_PM_CTRL_DATA_SCALE_MASK in next version. Sorry.

> 
>>      }
>>  }
>>  
>> @@ -2297,6 +2330,8 @@ static Property virtio_pci_properties[] = {
>>                      VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
>>      DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
>>                      VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
>> +    DEFINE_PROP_BIT("x-pcie-pm-no-soft-reset", VirtIOPCIProxy, flags,
>> +                    VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, true),
>>      DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
>>                      VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
>>      DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
>> diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h
>> index 59d88018c16a..9e67ba38c748 100644
>> --- a/include/hw/virtio/virtio-pci.h
>> +++ b/include/hw/virtio/virtio-pci.h
>> @@ -43,6 +43,7 @@ enum {
>>      VIRTIO_PCI_FLAG_INIT_FLR_BIT,
>>      VIRTIO_PCI_FLAG_AER_BIT,
>>      VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT,
>> +    VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT,
>>  };
>>  
>>  /* Need to activate work-arounds for buggy guests at vmstate load. */
>> @@ -79,6 +80,10 @@ enum {
>>  /* Init Power Management */
>>  #define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT)
>>  
>> +/* Init The No_Soft_Reset bit of Power Management */
>> +#define VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET \
>> +  (1 << VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT)
>> +
>>  /* Init Function Level Reset capability */
>>  #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
>>  
>> -- 
>> 2.34.1
> 

-- 
Best regards,
Jiqian Chen.