* [PATCH v3 0/5] Add support for Blaize BLZP1600 SoC
@ 2024-04-25 9:15 ` Niko Pasaloukos
0 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Adds basic support for the Blaize BLZP1600 SoC.
This SoC contains two cores of Cortex-A53 CPUs, one Blaize
Graph Streaming Processor (GSP) and several other IPs.
V3 changes:
* Removed unnecessary dt-bindings
* Update SoBs
V2 changes:
* Update SoBs
* `make dtbs_check` has no warnings
* Fix dts names and removed dead code
* DTS is separated from anything else
Nikolaos Pasaloukos (5):
dt-bindings: Add Blaize vendor prefix
dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
arm64: Add Blaize BLZP1600 SoC family
arm64: Add initial support for Blaize BLZP1600 CB2
arm64: defconfig: Enable ARCH_BLAIZE_BLZP1600
.../devicetree/bindings/arm/blaize.yaml | 40 ++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/Kconfig.platforms | 5 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/blaize/Makefile | 2 +
.../boot/dts/blaize/blaize-blzp1600-cb2.dts | 84 +++++++
.../boot/dts/blaize/blaize-blzp1600-som.dtsi | 23 ++
.../boot/dts/blaize/blaize-blzp1600.dtsi | 209 ++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
9 files changed, 367 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/blaize.yaml
create mode 100644 arch/arm64/boot/dts/blaize/Makefile
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
--
2.34.1
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v3 1/5] dt-bindings: Add Blaize vendor prefix
2024-04-25 9:15 ` Niko Pasaloukos
@ 2024-04-25 9:15 ` Niko Pasaloukos
-1 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Blaize, Inc. (www.blaize.com) is a SoC manufacturer with integrated
programmable Graph-Streaming-Processors for AI and ML.
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index b97d298b3eb6..746ff14028d1 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -214,6 +214,8 @@ patternProperties:
description: Shenzhen BigTree Tech Co., LTD
"^bitmain,.*":
description: Bitmain Technologies
+ "^blaize,.*":
+ description: Blaize, Inc.
"^blutek,.*":
description: BluTek Power
"^boe,.*":
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v3 1/5] dt-bindings: Add Blaize vendor prefix
@ 2024-04-25 9:15 ` Niko Pasaloukos
0 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Blaize, Inc. (www.blaize.com) is a SoC manufacturer with integrated
programmable Graph-Streaming-Processors for AI and ML.
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index b97d298b3eb6..746ff14028d1 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -214,6 +214,8 @@ patternProperties:
description: Shenzhen BigTree Tech Co., LTD
"^bitmain,.*":
description: Bitmain Technologies
+ "^blaize,.*":
+ description: Blaize, Inc.
"^blutek,.*":
description: BluTek Power
"^boe,.*":
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v3 1/5] dt-bindings: Add Blaize vendor prefix
2024-04-25 9:15 ` Niko Pasaloukos
@ 2024-04-25 16:33 ` Rob Herring
-1 siblings, 0 replies; 28+ messages in thread
From: Rob Herring @ 2024-04-25 16:33 UTC (permalink / raw)
To: Niko Pasaloukos
Cc: linux-kernel, andre.przywara, catalin.marinas, geert+renesas,
konrad.dybcio, u-kumar1, andersson, m.szyprowski, James Cowgill,
macromorgan, sre, Neil Jones, shawnguo, hvilleneuve, nfraprado,
arnd, conor+dt, will, Matt Redfearn, olof, krzysztof.kozlowski+dt,
heiko.stuebner, rafal, linus.walleij, devicetree,
linux-arm-kernel, neil.armstrong
On Thu, 25 Apr 2024 09:15:03 +0000, Niko Pasaloukos wrote:
> Blaize, Inc. (www.blaize.com) is a SoC manufacturer with integrated
> programmable Graph-Streaming-Processors for AI and ML.
>
> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: Add Blaize vendor prefix
@ 2024-04-25 16:33 ` Rob Herring
0 siblings, 0 replies; 28+ messages in thread
From: Rob Herring @ 2024-04-25 16:33 UTC (permalink / raw)
To: Niko Pasaloukos
Cc: linux-kernel, andre.przywara, catalin.marinas, geert+renesas,
konrad.dybcio, u-kumar1, andersson, m.szyprowski, James Cowgill,
macromorgan, sre, Neil Jones, shawnguo, hvilleneuve, nfraprado,
arnd, conor+dt, will, Matt Redfearn, olof, krzysztof.kozlowski+dt,
heiko.stuebner, rafal, linus.walleij, devicetree,
linux-arm-kernel, neil.armstrong
On Thu, 25 Apr 2024 09:15:03 +0000, Niko Pasaloukos wrote:
> Blaize, Inc. (www.blaize.com) is a SoC manufacturer with integrated
> programmable Graph-Streaming-Processors for AI and ML.
>
> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v3 2/5] dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
2024-04-25 9:15 ` Niko Pasaloukos
@ 2024-04-25 9:15 ` Niko Pasaloukos
-1 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Add device tree bindings for the Blaize BLZP1600 CB2
development board (carrier board), which uses the
BLZP1600 SoM.
Reviewed-by: James Cowgill <james.cowgill@blaize.com>
Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
Reviewed-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
.../devicetree/bindings/arm/blaize.yaml | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/blaize.yaml
diff --git a/Documentation/devicetree/bindings/arm/blaize.yaml b/Documentation/devicetree/bindings/arm/blaize.yaml
new file mode 100644
index 000000000000..8034aeb7a2b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/blaize.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/blaize.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Blaize Platforms
+
+maintainers:
+ - James Cowgill <james.cowgill@blaize.com>
+ - Matt Redfearn <matt.redfearn@blaize.com>
+ - Neil Jones <neil.jones@blaize.com>
+ - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
+
+description: |
+ Blaize Platforms using SoCs designed by Blaize Inc.
+
+ The products currently based on the BLZP1600 SoC:
+
+ - BLZP1600-SoM: SoM module
+ - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
+
+ The compatible property should follow the format:
+
+ compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Blaize BLZP1600 based boards
+ items:
+ - enum:
+ - blaize,blzp1600-cb2
+ - const: blaize,blzp1600
+
+additionalProperties: true
+
+...
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 2/5] dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
@ 2024-04-25 9:15 ` Niko Pasaloukos
0 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Add device tree bindings for the Blaize BLZP1600 CB2
development board (carrier board), which uses the
BLZP1600 SoM.
Reviewed-by: James Cowgill <james.cowgill@blaize.com>
Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
Reviewed-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
.../devicetree/bindings/arm/blaize.yaml | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/blaize.yaml
diff --git a/Documentation/devicetree/bindings/arm/blaize.yaml b/Documentation/devicetree/bindings/arm/blaize.yaml
new file mode 100644
index 000000000000..8034aeb7a2b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/blaize.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/blaize.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Blaize Platforms
+
+maintainers:
+ - James Cowgill <james.cowgill@blaize.com>
+ - Matt Redfearn <matt.redfearn@blaize.com>
+ - Neil Jones <neil.jones@blaize.com>
+ - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
+
+description: |
+ Blaize Platforms using SoCs designed by Blaize Inc.
+
+ The products currently based on the BLZP1600 SoC:
+
+ - BLZP1600-SoM: SoM module
+ - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
+
+ The compatible property should follow the format:
+
+ compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Blaize BLZP1600 based boards
+ items:
+ - enum:
+ - blaize,blzp1600-cb2
+ - const: blaize,blzp1600
+
+additionalProperties: true
+
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
2024-04-25 9:15 ` Niko Pasaloukos
@ 2024-04-25 9:16 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 9:16 UTC (permalink / raw)
To: Niko Pasaloukos, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On 25/04/2024 11:15, Niko Pasaloukos wrote:
> Add device tree bindings for the Blaize BLZP1600 CB2
> development board (carrier board), which uses the
> BLZP1600 SoM.
>
> Reviewed-by: James Cowgill <james.cowgill@blaize.com>
> Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
> Reviewed-by: Neil Jones <neil.jones@blaize.com>
> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> ---
> .../devicetree/bindings/arm/blaize.yaml | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/blaize.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/blaize.yaml b/Documentation/devicetree/bindings/arm/blaize.yaml
> new file mode 100644
> index 000000000000..8034aeb7a2b4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/blaize.yaml
> @@ -0,0 +1,40 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/blaize.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Blaize Platforms
> +
> +maintainers:
> + - James Cowgill <james.cowgill@blaize.com>
> + - Matt Redfearn <matt.redfearn@blaize.com>
> + - Neil Jones <neil.jones@blaize.com>
> + - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> +
> +description: |
> + Blaize Platforms using SoCs designed by Blaize Inc.
> +
> + The products currently based on the BLZP1600 SoC:
> +
> + - BLZP1600-SoM: SoM module
> + - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
> +
> + The compatible property should follow the format:
> +
> + compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
This is a friendly reminder during the review process.
It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
@ 2024-04-25 9:16 ` Krzysztof Kozlowski
0 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 9:16 UTC (permalink / raw)
To: Niko Pasaloukos, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On 25/04/2024 11:15, Niko Pasaloukos wrote:
> Add device tree bindings for the Blaize BLZP1600 CB2
> development board (carrier board), which uses the
> BLZP1600 SoM.
>
> Reviewed-by: James Cowgill <james.cowgill@blaize.com>
> Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
> Reviewed-by: Neil Jones <neil.jones@blaize.com>
> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> ---
> .../devicetree/bindings/arm/blaize.yaml | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/blaize.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/blaize.yaml b/Documentation/devicetree/bindings/arm/blaize.yaml
> new file mode 100644
> index 000000000000..8034aeb7a2b4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/blaize.yaml
> @@ -0,0 +1,40 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/blaize.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Blaize Platforms
> +
> +maintainers:
> + - James Cowgill <james.cowgill@blaize.com>
> + - Matt Redfearn <matt.redfearn@blaize.com>
> + - Neil Jones <neil.jones@blaize.com>
> + - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> +
> +description: |
> + Blaize Platforms using SoCs designed by Blaize Inc.
> +
> + The products currently based on the BLZP1600 SoC:
> +
> + - BLZP1600-SoM: SoM module
> + - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
> +
> + The compatible property should follow the format:
> +
> + compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
This is a friendly reminder during the review process.
It seems my or other reviewer's previous comments were not fully
addressed. Maybe the feedback got lost between the quotes, maybe you
just forgot to apply it. Please go back to the previous discussion and
either implement all requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
2024-04-25 9:16 ` Krzysztof Kozlowski
@ 2024-04-25 9:20 ` Nikolaos Pasaloukos
-1 siblings, 0 replies; 28+ messages in thread
From: Nikolaos Pasaloukos @ 2024-04-25 9:20 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On 25/04/2024 10:16, Krzysztof Kozlowski wrote:
> On 25/04/2024 11:15, Niko Pasaloukos wrote:
>> Add device tree bindings for the Blaize BLZP1600 CB2
>> development board (carrier board), which uses the
>> BLZP1600 SoM.
>>
>> Reviewed-by: James Cowgill <james.cowgill@blaize.com>
>> Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
>> Reviewed-by: Neil Jones <neil.jones@blaize.com>
>> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
>> ---
>> .../devicetree/bindings/arm/blaize.yaml | 40 +++++++++++++++++++
>> 1 file changed, 40 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/blaize.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/blaize.yaml b/Documentation/devicetree/bindings/arm/blaize.yaml
>> new file mode 100644
>> index 000000000000..8034aeb7a2b4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/blaize.yaml
>> @@ -0,0 +1,40 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/arm/blaize.yaml*__;Iw!!FddXBOku!i6XKbnL3gXmoklJKfuksrfCB61MTEFuw8JiIVn9sS0CzEmHpqDhXguC5Me3sUQt1gw4RxA4mo8TAHR8psxBV0Dmrs0veWKlRgo18$
>> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!FddXBOku!i6XKbnL3gXmoklJKfuksrfCB61MTEFuw8JiIVn9sS0CzEmHpqDhXguC5Me3sUQt1gw4RxA4mo8TAHR8psxBV0Dmrs0veWEVjMhqf$
>> +
>> +title: Blaize Platforms
>> +
>> +maintainers:
>> + - James Cowgill <james.cowgill@blaize.com>
>> + - Matt Redfearn <matt.redfearn@blaize.com>
>> + - Neil Jones <neil.jones@blaize.com>
>> + - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
>> +
>> +description: |
>> + Blaize Platforms using SoCs designed by Blaize Inc.
>> +
>> + The products currently based on the BLZP1600 SoC:
>> +
>> + - BLZP1600-SoM: SoM module
>> + - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
>> +
>> + The compatible property should follow the format:
>> +
>> + compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
>
> This is a friendly reminder during the review process.
>
> It seems my or other reviewer's previous comments were not fully
> addressed. Maybe the feedback got lost between the quotes, maybe you
> just forgot to apply it. Please go back to the previous discussion and
> either implement all requested changes or keep discussing them.
>
> Thank you.
>
> Best regards,
> Krzysztof
>
Apologies, you are right. Now with the threading fixed, I'll be able to gather all the feedback properly.
I'll fix this on V4.
Best regards,
Niko
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
@ 2024-04-25 9:20 ` Nikolaos Pasaloukos
0 siblings, 0 replies; 28+ messages in thread
From: Nikolaos Pasaloukos @ 2024-04-25 9:20 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On 25/04/2024 10:16, Krzysztof Kozlowski wrote:
> On 25/04/2024 11:15, Niko Pasaloukos wrote:
>> Add device tree bindings for the Blaize BLZP1600 CB2
>> development board (carrier board), which uses the
>> BLZP1600 SoM.
>>
>> Reviewed-by: James Cowgill <james.cowgill@blaize.com>
>> Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
>> Reviewed-by: Neil Jones <neil.jones@blaize.com>
>> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
>> ---
>> .../devicetree/bindings/arm/blaize.yaml | 40 +++++++++++++++++++
>> 1 file changed, 40 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/blaize.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/blaize.yaml b/Documentation/devicetree/bindings/arm/blaize.yaml
>> new file mode 100644
>> index 000000000000..8034aeb7a2b4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/blaize.yaml
>> @@ -0,0 +1,40 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/arm/blaize.yaml*__;Iw!!FddXBOku!i6XKbnL3gXmoklJKfuksrfCB61MTEFuw8JiIVn9sS0CzEmHpqDhXguC5Me3sUQt1gw4RxA4mo8TAHR8psxBV0Dmrs0veWKlRgo18$
>> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!FddXBOku!i6XKbnL3gXmoklJKfuksrfCB61MTEFuw8JiIVn9sS0CzEmHpqDhXguC5Me3sUQt1gw4RxA4mo8TAHR8psxBV0Dmrs0veWEVjMhqf$
>> +
>> +title: Blaize Platforms
>> +
>> +maintainers:
>> + - James Cowgill <james.cowgill@blaize.com>
>> + - Matt Redfearn <matt.redfearn@blaize.com>
>> + - Neil Jones <neil.jones@blaize.com>
>> + - Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
>> +
>> +description: |
>> + Blaize Platforms using SoCs designed by Blaize Inc.
>> +
>> + The products currently based on the BLZP1600 SoC:
>> +
>> + - BLZP1600-SoM: SoM module
>> + - BLZP1600-CB2: Development board CB2 based on BLZP1600-SoM
>> +
>> + The compatible property should follow the format:
>> +
>> + compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
>
> This is a friendly reminder during the review process.
>
> It seems my or other reviewer's previous comments were not fully
> addressed. Maybe the feedback got lost between the quotes, maybe you
> just forgot to apply it. Please go back to the previous discussion and
> either implement all requested changes or keep discussing them.
>
> Thank you.
>
> Best regards,
> Krzysztof
>
Apologies, you are right. Now with the threading fixed, I'll be able to gather all the feedback properly.
I'll fix this on V4.
Best regards,
Niko
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v3 3/5] arm64: Add Blaize BLZP1600 SoC family
2024-04-25 9:15 ` Niko Pasaloukos
@ 2024-04-25 9:15 ` Niko Pasaloukos
-1 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Add ARCH_BLAIZE_BLZP1600 SoC family to the arm64 architecture.
Reviewed-by: James Cowgill <james.cowgill@blaize.com>
Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
Reviewed-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
arch/arm64/Kconfig.platforms | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 24335565bad5..c2a523637b23 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -94,6 +94,11 @@ config ARCH_BITMAIN
help
This enables support for the Bitmain SoC Family.
+config ARCH_BLAIZE_BLZP1600
+ bool "Blaize BLZP1600 SoC Platforms"
+ help
+ This enables support for the Blaize BLZP1600 SoC family
+
config ARCH_EXYNOS
bool "Samsung Exynos SoC family"
select COMMON_CLK_SAMSUNG
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 3/5] arm64: Add Blaize BLZP1600 SoC family
@ 2024-04-25 9:15 ` Niko Pasaloukos
0 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Add ARCH_BLAIZE_BLZP1600 SoC family to the arm64 architecture.
Reviewed-by: James Cowgill <james.cowgill@blaize.com>
Reviewed-by: Matt Redfearn <matt.redfearn@blaize.com>
Reviewed-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
arch/arm64/Kconfig.platforms | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 24335565bad5..c2a523637b23 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -94,6 +94,11 @@ config ARCH_BITMAIN
help
This enables support for the Bitmain SoC Family.
+config ARCH_BLAIZE_BLZP1600
+ bool "Blaize BLZP1600 SoC Platforms"
+ help
+ This enables support for the Blaize BLZP1600 SoC family
+
config ARCH_EXYNOS
bool "Samsung Exynos SoC family"
select COMMON_CLK_SAMSUNG
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
2024-04-25 9:15 ` Niko Pasaloukos
@ 2024-04-25 9:15 ` Niko Pasaloukos
-1 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Adds support for the Blaize CB2 development board based on
BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.
The blaize-blzp1600.dtsi is the common part for the SoC,
blaize-blzp1600-som.dtsi is the common part for the SoM and
blaize-blzp1600-cb2.dts is the board specific file.
Co-developed-by: James Cowgill <james.cowgill@blaize.com>
Signed-off-by: James Cowgill <james.cowgill@blaize.com>
Co-developed-by: Matt Redfearn <matt.redfearn@blaize.com>
Signed-off-by: Matt Redfearn <matt.redfearn@blaize.com>
Co-developed-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/blaize/Makefile | 2 +
.../boot/dts/blaize/blaize-blzp1600-cb2.dts | 84 +++++++
.../boot/dts/blaize/blaize-blzp1600-som.dtsi | 23 ++
.../boot/dts/blaize/blaize-blzp1600.dtsi | 209 ++++++++++++++++++
5 files changed, 319 insertions(+)
create mode 100644 arch/arm64/boot/dts/blaize/Makefile
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 30dd6347a929..601b6381ea0c 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += apm
subdir-y += apple
subdir-y += arm
subdir-y += bitmain
+subdir-y += blaize
subdir-y += broadcom
subdir-y += cavium
subdir-y += exynos
diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blaize/Makefile
new file mode 100644
index 000000000000..595e7a350300
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_BLAIZE_BLZP1600) += blaize-blzp1600-cb2.dtb
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
new file mode 100644
index 000000000000..0bdec7e81380
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "blaize-blzp1600-som.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
+
+ compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200";
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ gpio_expander: gpio@74 {
+ compatible = "ti,tca9539";
+ reg = <0x74>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "RSP_PIN_7", /* GPIO_0 */
+ "RSP_PIN_11", /* GPIO_1 */
+ "RSP_PIN_13", /* GPIO_2 */
+ "RSP_PIN_15", /* GPIO_3 */
+ "RSP_PIN_27", /* GPIO_4 */
+ "RSP_PIN_29", /* GPIO_5 */
+ "RSP_PIN_31", /* GPIO_6 */
+ "RSP_PIN_33", /* GPIO_7 */
+ "RSP_PIN_37", /* GPIO_8 */
+ "RSP_PIN_16", /* GPIO_9 */
+ "RSP_PIN_18", /* GPIO_10 */
+ "RSP_PIN_22", /* GPIO_11 */
+ "RSP_PIN_28", /* GPIO_12 */
+ "RSP_PIN_32", /* GPIO_13 */
+ "RSP_PIN_36", /* GPIO_14 */
+ "TP31"; /* GPIO_15 */
+ };
+
+ gpio_expander_m2: gpio@75 {
+ compatible = "ti,tca9539";
+ reg = <0x75>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */
+ "M2_W_DIS2_N", /* GPIO_1 */
+ "M2_UART_WAKE_N", /* GPIO_2 */
+ "M2_COEX3", /* GPIO_3 */
+ "M2_COEX_RXD", /* GPIO_4 */
+ "M2_COEX_TXD", /* GPIO_5 */
+ "M2_VENDOR_PIN40", /* GPIO_6 */
+ "M2_VENDOR_PIN42", /* GPIO_7 */
+ "M2_VENDOR_PIN38", /* GPIO_8 */
+ "M2_SDIO_RST_N", /* GPIO_9 */
+ "M2_SDIO_WAKE_N", /* GPIO_10 */
+ "M2_PETN1", /* GPIO_11 */
+ "M2_PERP1", /* GPIO_12 */
+ "M2_PERN1", /* GPIO_13 */
+ "UIM_SWP", /* GPIO_14 */
+ "UART1_TO_RSP"; /* GPIO_15 */
+ };
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
new file mode 100644
index 000000000000..efac0d6b3d60
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+#include "blaize-blzp1600.dtsi"
+
+/ {
+ memory@1000 {
+ device_type = "memory";
+ reg = <0x0 0x00001000 0xfffff000>;
+ };
+};
+
+/* i2c4 bus is available only on the SoM, not on the board */
+&i2c4 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
new file mode 100644
index 000000000000..26d8943d60ab
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0 0x0>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0 0x1>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = /* Physical Secure PPI */
+ <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ /* Physical Non-Secure PPI */
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ /* Hypervisor PPI */
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ /* Virtual PPI */
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+
+ sram@0 {
+ /*
+ * On BLZP1600 there is no general purpose (non-secure) SRAM.
+ * A small DDR memory space has been reserved for general use.
+ */
+ compatible = "mmio-sram";
+ reg = <0x0 0x00000000 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x00000000 0x1000>;
+
+ /* SCMI reserved buffer space on DDR space */
+ scmi0_shm: scmi-sram@800 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x800 0x80>;
+ };
+ };
+
+ firmware {
+ scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82002000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ shmem = <&scmi0_shm>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ gic: interrupt-controller@200410000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2 0x00410000 0x20000>,
+ <0x2 0x00420000 0x20000>,
+ <0x2 0x00440000 0x20000>,
+ <0x2 0x00460000 0x20000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ uart0: serial@2004d0000 {
+ compatible = "ns16550a";
+ reg = <0x2 0x004d0000 0x1000>;
+ clocks = <&scmi_clk 59>;
+ resets = <&scmi_rst 59>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart1: serial@2004e0000 {
+ compatible = "ns16550a";
+ reg = <0x2 0x004e0000 0x1000>;
+ clocks = <&scmi_clk 60>;
+ resets = <&scmi_rst 60>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2004f0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x004f0000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 54>;
+ resets = <&scmi_rst 54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@200500000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00500000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 55>;
+ resets = <&scmi_rst 55>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@200510000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00510000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 56>;
+ resets = <&scmi_rst 56>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@200520000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00520000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 57>;
+ resets = <&scmi_rst 57>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@200530000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00530000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 58>;
+ resets = <&scmi_rst 58>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ arm_cc712: crypto@200550000 {
+ compatible = "arm,cryptocell-712-ree";
+ reg = <0x2 0x00550000 0x1000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 7>;
+ };
+ };
+};
--
2.34.1
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^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
@ 2024-04-25 9:15 ` Niko Pasaloukos
0 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Adds support for the Blaize CB2 development board based on
BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.
The blaize-blzp1600.dtsi is the common part for the SoC,
blaize-blzp1600-som.dtsi is the common part for the SoM and
blaize-blzp1600-cb2.dts is the board specific file.
Co-developed-by: James Cowgill <james.cowgill@blaize.com>
Signed-off-by: James Cowgill <james.cowgill@blaize.com>
Co-developed-by: Matt Redfearn <matt.redfearn@blaize.com>
Signed-off-by: Matt Redfearn <matt.redfearn@blaize.com>
Co-developed-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Neil Jones <neil.jones@blaize.com>
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/blaize/Makefile | 2 +
.../boot/dts/blaize/blaize-blzp1600-cb2.dts | 84 +++++++
.../boot/dts/blaize/blaize-blzp1600-som.dtsi | 23 ++
.../boot/dts/blaize/blaize-blzp1600.dtsi | 209 ++++++++++++++++++
5 files changed, 319 insertions(+)
create mode 100644 arch/arm64/boot/dts/blaize/Makefile
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 30dd6347a929..601b6381ea0c 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -9,6 +9,7 @@ subdir-y += apm
subdir-y += apple
subdir-y += arm
subdir-y += bitmain
+subdir-y += blaize
subdir-y += broadcom
subdir-y += cavium
subdir-y += exynos
diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blaize/Makefile
new file mode 100644
index 000000000000..595e7a350300
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_BLAIZE_BLZP1600) += blaize-blzp1600-cb2.dtb
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
new file mode 100644
index 000000000000..0bdec7e81380
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "blaize-blzp1600-som.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
+
+ compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200";
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ gpio_expander: gpio@74 {
+ compatible = "ti,tca9539";
+ reg = <0x74>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "RSP_PIN_7", /* GPIO_0 */
+ "RSP_PIN_11", /* GPIO_1 */
+ "RSP_PIN_13", /* GPIO_2 */
+ "RSP_PIN_15", /* GPIO_3 */
+ "RSP_PIN_27", /* GPIO_4 */
+ "RSP_PIN_29", /* GPIO_5 */
+ "RSP_PIN_31", /* GPIO_6 */
+ "RSP_PIN_33", /* GPIO_7 */
+ "RSP_PIN_37", /* GPIO_8 */
+ "RSP_PIN_16", /* GPIO_9 */
+ "RSP_PIN_18", /* GPIO_10 */
+ "RSP_PIN_22", /* GPIO_11 */
+ "RSP_PIN_28", /* GPIO_12 */
+ "RSP_PIN_32", /* GPIO_13 */
+ "RSP_PIN_36", /* GPIO_14 */
+ "TP31"; /* GPIO_15 */
+ };
+
+ gpio_expander_m2: gpio@75 {
+ compatible = "ti,tca9539";
+ reg = <0x75>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */
+ "M2_W_DIS2_N", /* GPIO_1 */
+ "M2_UART_WAKE_N", /* GPIO_2 */
+ "M2_COEX3", /* GPIO_3 */
+ "M2_COEX_RXD", /* GPIO_4 */
+ "M2_COEX_TXD", /* GPIO_5 */
+ "M2_VENDOR_PIN40", /* GPIO_6 */
+ "M2_VENDOR_PIN42", /* GPIO_7 */
+ "M2_VENDOR_PIN38", /* GPIO_8 */
+ "M2_SDIO_RST_N", /* GPIO_9 */
+ "M2_SDIO_WAKE_N", /* GPIO_10 */
+ "M2_PETN1", /* GPIO_11 */
+ "M2_PERP1", /* GPIO_12 */
+ "M2_PERN1", /* GPIO_13 */
+ "UIM_SWP", /* GPIO_14 */
+ "UART1_TO_RSP"; /* GPIO_15 */
+ };
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
new file mode 100644
index 000000000000..efac0d6b3d60
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+#include "blaize-blzp1600.dtsi"
+
+/ {
+ memory@1000 {
+ device_type = "memory";
+ reg = <0x0 0x00001000 0xfffff000>;
+ };
+};
+
+/* i2c4 bus is available only on the SoM, not on the board */
+&i2c4 {
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
new file mode 100644
index 000000000000..26d8943d60ab
--- /dev/null
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Blaize, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0 0x0>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0 0x1>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = /* Physical Secure PPI */
+ <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ /* Physical Non-Secure PPI */
+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ /* Hypervisor PPI */
+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ /* Virtual PPI */
+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ };
+
+ sram@0 {
+ /*
+ * On BLZP1600 there is no general purpose (non-secure) SRAM.
+ * A small DDR memory space has been reserved for general use.
+ */
+ compatible = "mmio-sram";
+ reg = <0x0 0x00000000 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x00000000 0x1000>;
+
+ /* SCMI reserved buffer space on DDR space */
+ scmi0_shm: scmi-sram@800 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x800 0x80>;
+ };
+ };
+
+ firmware {
+ scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82002000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ shmem = <&scmi0_shm>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_rst: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ gic: interrupt-controller@200410000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x2 0x00410000 0x20000>,
+ <0x2 0x00420000 0x20000>,
+ <0x2 0x00440000 0x20000>,
+ <0x2 0x00460000 0x20000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x3) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ uart0: serial@2004d0000 {
+ compatible = "ns16550a";
+ reg = <0x2 0x004d0000 0x1000>;
+ clocks = <&scmi_clk 59>;
+ resets = <&scmi_rst 59>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart1: serial@2004e0000 {
+ compatible = "ns16550a";
+ reg = <0x2 0x004e0000 0x1000>;
+ clocks = <&scmi_clk 60>;
+ resets = <&scmi_rst 60>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2004f0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x004f0000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 54>;
+ resets = <&scmi_rst 54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@200500000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00500000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 55>;
+ resets = <&scmi_rst 55>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@200510000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00510000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 56>;
+ resets = <&scmi_rst 56>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@200520000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00520000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 57>;
+ resets = <&scmi_rst 57>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@200530000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2 0x00530000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 58>;
+ resets = <&scmi_rst 58>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ arm_cc712: crypto@200550000 {
+ compatible = "arm,cryptocell-712-ree";
+ reg = <0x2 0x00550000 0x1000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk 7>;
+ };
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
2024-04-25 9:15 ` Niko Pasaloukos
@ 2024-04-25 9:21 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 9:21 UTC (permalink / raw)
To: Niko Pasaloukos, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On 25/04/2024 11:15, Niko Pasaloukos wrote:
> Adds support for the Blaize CB2 development board based on
> BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.
Subject: missing dts prefix.
...
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0 0x0>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0 0x1>;
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache0 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = /* Physical Secure PPI */
> + <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Physical Non-Secure PPI */
> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Hypervisor PPI */
> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Virtual PPI */
> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + pmu {
Nodes in top-level look randomly ordered. Any reason why not using DTS
coding style in this regard?
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>;
> + };
> +
> + sram@0 {
> + /*
> + * On BLZP1600 there is no general purpose (non-secure) SRAM.
> + * A small DDR memory space has been reserved for general use.
> + */
> + compatible = "mmio-sram";
> + reg = <0x0 0x00000000 0x00001000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x00000000 0x1000>;
ranges follow reg
> +
> + /* SCMI reserved buffer space on DDR space */
> + scmi0_shm: scmi-sram@800 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x800 0x80>;
> + };
> + };
> +
> + firmware {
> + scmi {
> + compatible = "arm,scmi-smc";
> + arm,smc-id = <0x82002000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + shmem = <&scmi0_shm>;
> +
> + scmi_clk: protocol@14 {
> + reg = <0x14>;
> + #clock-cells = <1>;
> + };
> +
> + scmi_rst: protocol@16 {
> + reg = <0x16>;
> + #reset-cells = <1>;
> + };
> + };
> + };
> +
> + soc {
This does not cause dtbs_check W=1 warnings? Surprising a bit... This
should cause big fat warning, so I have doubts patchset was tested.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
@ 2024-04-25 9:21 ` Krzysztof Kozlowski
0 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 9:21 UTC (permalink / raw)
To: Niko Pasaloukos, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On 25/04/2024 11:15, Niko Pasaloukos wrote:
> Adds support for the Blaize CB2 development board based on
> BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.
Subject: missing dts prefix.
...
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0 0x0>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0 0x1>;
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache0 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = /* Physical Secure PPI */
> + <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Physical Non-Secure PPI */
> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Hypervisor PPI */
> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Virtual PPI */
> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + pmu {
Nodes in top-level look randomly ordered. Any reason why not using DTS
coding style in this regard?
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>;
> + };
> +
> + sram@0 {
> + /*
> + * On BLZP1600 there is no general purpose (non-secure) SRAM.
> + * A small DDR memory space has been reserved for general use.
> + */
> + compatible = "mmio-sram";
> + reg = <0x0 0x00000000 0x00001000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x00000000 0x1000>;
ranges follow reg
> +
> + /* SCMI reserved buffer space on DDR space */
> + scmi0_shm: scmi-sram@800 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x800 0x80>;
> + };
> + };
> +
> + firmware {
> + scmi {
> + compatible = "arm,scmi-smc";
> + arm,smc-id = <0x82002000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + shmem = <&scmi0_shm>;
> +
> + scmi_clk: protocol@14 {
> + reg = <0x14>;
> + #clock-cells = <1>;
> + };
> +
> + scmi_rst: protocol@16 {
> + reg = <0x16>;
> + #reset-cells = <1>;
> + };
> + };
> + };
> +
> + soc {
This does not cause dtbs_check W=1 warnings? Surprising a bit... This
should cause big fat warning, so I have doubts patchset was tested.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
2024-04-25 9:21 ` Krzysztof Kozlowski
@ 2024-04-25 10:41 ` Nikolaos Pasaloukos
-1 siblings, 0 replies; 28+ messages in thread
From: Nikolaos Pasaloukos @ 2024-04-25 10:41 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On 25/04/2024 10:21, Krzysztof Kozlowski wrote:
> On 25/04/2024 11:15, Niko Pasaloukos wrote:
>> Adds support for the Blaize CB2 development board based on
>> BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.
>
> Subject: missing dts prefix.
>
>
> ...
>
>> +
>> +/ {
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + compatible = "arm,cortex-a53";
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + reg = <0x0 0x0>;
>> + next-level-cache = <&l2>;
>> + };
>> +
>> + cpu1: cpu@1 {
>> + compatible = "arm,cortex-a53";
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + reg = <0x0 0x1>;
>> + next-level-cache = <&l2>;
>> + };
>> +
>> + l2: l2-cache0 {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = /* Physical Secure PPI */
>> + <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
>> + IRQ_TYPE_LEVEL_LOW)>,
>> + /* Physical Non-Secure PPI */
>> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
>> + IRQ_TYPE_LEVEL_LOW)>,
>> + /* Hypervisor PPI */
>> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
>> + IRQ_TYPE_LEVEL_LOW)>,
>> + /* Virtual PPI */
>> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
>> + IRQ_TYPE_LEVEL_LOW)>;
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0", "arm,psci-0.2";
>> + method = "smc";
>> + };
>> +
>> + pmu {
>
> Nodes in top-level look randomly ordered. Any reason why not using DTS
> coding style in this regard?
>
>> + compatible = "arm,cortex-a53-pmu";
>> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-affinity = <&cpu0>, <&cpu1>;
>> + };
>> +
>> + sram@0 {
>> + /*
>> + * On BLZP1600 there is no general purpose (non-secure) SRAM.
>> + * A small DDR memory space has been reserved for general use.
>> + */
>> + compatible = "mmio-sram";
>> + reg = <0x0 0x00000000 0x00001000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x0 0x00000000 0x1000>;
>
> ranges follow reg
>
>> +
>> + /* SCMI reserved buffer space on DDR space */
>> + scmi0_shm: scmi-sram@800 {
>> + compatible = "arm,scmi-shmem";
>> + reg = <0x800 0x80>;
>> + };
>> + };
>> +
>> + firmware {
>> + scmi {
>> + compatible = "arm,scmi-smc";
>> + arm,smc-id = <0x82002000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + shmem = <&scmi0_shm>;
>> +
>> + scmi_clk: protocol@14 {
>> + reg = <0x14>;
>> + #clock-cells = <1>;
>> + };
>> +
>> + scmi_rst: protocol@16 {
>> + reg = <0x16>;
>> + #reset-cells = <1>;
>> + };
>> + };
>> + };
>> +
>> + soc {
>
> This does not cause dtbs_check W=1 warnings? Surprising a bit... This
> should cause big fat warning, so I have doubts patchset was tested.
>
>
> Best regards,
> Krzysztof
>
No it doesn't cause any warnings. I did:
make arch=arm64 dt_binding_check
make arch=arm64 dtbs_check W=1
I don't get any warnings. Could you please let me know what kind of
warning I should get? Am I doing something wrong and I don't get
the warning?
Kind regards,
Niko
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
@ 2024-04-25 10:41 ` Nikolaos Pasaloukos
0 siblings, 0 replies; 28+ messages in thread
From: Nikolaos Pasaloukos @ 2024-04-25 10:41 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On 25/04/2024 10:21, Krzysztof Kozlowski wrote:
> On 25/04/2024 11:15, Niko Pasaloukos wrote:
>> Adds support for the Blaize CB2 development board based on
>> BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.
>
> Subject: missing dts prefix.
>
>
> ...
>
>> +
>> +/ {
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + compatible = "arm,cortex-a53";
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + reg = <0x0 0x0>;
>> + next-level-cache = <&l2>;
>> + };
>> +
>> + cpu1: cpu@1 {
>> + compatible = "arm,cortex-a53";
>> + device_type = "cpu";
>> + enable-method = "psci";
>> + reg = <0x0 0x1>;
>> + next-level-cache = <&l2>;
>> + };
>> +
>> + l2: l2-cache0 {
>> + compatible = "cache";
>> + cache-level = <2>;
>> + cache-unified;
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = /* Physical Secure PPI */
>> + <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
>> + IRQ_TYPE_LEVEL_LOW)>,
>> + /* Physical Non-Secure PPI */
>> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
>> + IRQ_TYPE_LEVEL_LOW)>,
>> + /* Hypervisor PPI */
>> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
>> + IRQ_TYPE_LEVEL_LOW)>,
>> + /* Virtual PPI */
>> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
>> + IRQ_TYPE_LEVEL_LOW)>;
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0", "arm,psci-0.2";
>> + method = "smc";
>> + };
>> +
>> + pmu {
>
> Nodes in top-level look randomly ordered. Any reason why not using DTS
> coding style in this regard?
>
>> + compatible = "arm,cortex-a53-pmu";
>> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-affinity = <&cpu0>, <&cpu1>;
>> + };
>> +
>> + sram@0 {
>> + /*
>> + * On BLZP1600 there is no general purpose (non-secure) SRAM.
>> + * A small DDR memory space has been reserved for general use.
>> + */
>> + compatible = "mmio-sram";
>> + reg = <0x0 0x00000000 0x00001000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x0 0x00000000 0x1000>;
>
> ranges follow reg
>
>> +
>> + /* SCMI reserved buffer space on DDR space */
>> + scmi0_shm: scmi-sram@800 {
>> + compatible = "arm,scmi-shmem";
>> + reg = <0x800 0x80>;
>> + };
>> + };
>> +
>> + firmware {
>> + scmi {
>> + compatible = "arm,scmi-smc";
>> + arm,smc-id = <0x82002000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + shmem = <&scmi0_shm>;
>> +
>> + scmi_clk: protocol@14 {
>> + reg = <0x14>;
>> + #clock-cells = <1>;
>> + };
>> +
>> + scmi_rst: protocol@16 {
>> + reg = <0x16>;
>> + #reset-cells = <1>;
>> + };
>> + };
>> + };
>> +
>> + soc {
>
> This does not cause dtbs_check W=1 warnings? Surprising a bit... This
> should cause big fat warning, so I have doubts patchset was tested.
>
>
> Best regards,
> Krzysztof
>
No it doesn't cause any warnings. I did:
make arch=arm64 dt_binding_check
make arch=arm64 dtbs_check W=1
I don't get any warnings. Could you please let me know what kind of
warning I should get? Am I doing something wrong and I don't get
the warning?
Kind regards,
Niko
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
2024-04-25 10:41 ` Nikolaos Pasaloukos
@ 2024-04-25 11:09 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 11:09 UTC (permalink / raw)
To: Nikolaos Pasaloukos, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On 25/04/2024 12:41, Nikolaos Pasaloukos wrote:
>>> +
>>> + soc {
>>
>> This does not cause dtbs_check W=1 warnings? Surprising a bit... This
>> should cause big fat warning, so I have doubts patchset was tested.
>>
>>
>> Best regards,
>> Krzysztof
>>
>
> No it doesn't cause any warnings. I did:
> make arch=arm64 dt_binding_check
> make arch=arm64 dtbs_check W=1
> I don't get any warnings. Could you please let me know what kind of
> warning I should get? Am I doing something wrong and I don't get
> the warning?
I was expecting one for missing soc unit address, but you are right -
your ranges are empty, so "soc" is ok. I keep forgetting that
distinction. Looks fine then.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
@ 2024-04-25 11:09 ` Krzysztof Kozlowski
0 siblings, 0 replies; 28+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 11:09 UTC (permalink / raw)
To: Nikolaos Pasaloukos, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On 25/04/2024 12:41, Nikolaos Pasaloukos wrote:
>>> +
>>> + soc {
>>
>> This does not cause dtbs_check W=1 warnings? Surprising a bit... This
>> should cause big fat warning, so I have doubts patchset was tested.
>>
>>
>> Best regards,
>> Krzysztof
>>
>
> No it doesn't cause any warnings. I did:
> make arch=arm64 dt_binding_check
> make arch=arm64 dtbs_check W=1
> I don't get any warnings. Could you please let me know what kind of
> warning I should get? Am I doing something wrong and I don't get
> the warning?
I was expecting one for missing soc unit address, but you are right -
your ranges are empty, so "soc" is ok. I keep forgetting that
distinction. Looks fine then.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
2024-04-25 9:15 ` Niko Pasaloukos
@ 2024-04-25 16:56 ` Rob Herring
-1 siblings, 0 replies; 28+ messages in thread
From: Rob Herring @ 2024-04-25 16:56 UTC (permalink / raw)
To: Niko Pasaloukos
Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On Thu, Apr 25, 2024 at 4:15 AM Niko Pasaloukos
<nikolaos.pasaloukos@blaize.com> wrote:
>
> Adds support for the Blaize CB2 development board based on
> BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.
>
> The blaize-blzp1600.dtsi is the common part for the SoC,
> blaize-blzp1600-som.dtsi is the common part for the SoM and
> blaize-blzp1600-cb2.dts is the board specific file.
>
> Co-developed-by: James Cowgill <james.cowgill@blaize.com>
> Signed-off-by: James Cowgill <james.cowgill@blaize.com>
> Co-developed-by: Matt Redfearn <matt.redfearn@blaize.com>
> Signed-off-by: Matt Redfearn <matt.redfearn@blaize.com>
> Co-developed-by: Neil Jones <neil.jones@blaize.com>
> Signed-off-by: Neil Jones <neil.jones@blaize.com>
> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/blaize/Makefile | 2 +
> .../boot/dts/blaize/blaize-blzp1600-cb2.dts | 84 +++++++
> .../boot/dts/blaize/blaize-blzp1600-som.dtsi | 23 ++
> .../boot/dts/blaize/blaize-blzp1600.dtsi | 209 ++++++++++++++++++
> 5 files changed, 319 insertions(+)
> create mode 100644 arch/arm64/boot/dts/blaize/Makefile
> create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
> create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
> create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..601b6381ea0c 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ subdir-y += apm
> subdir-y += apple
> subdir-y += arm
> subdir-y += bitmain
> +subdir-y += blaize
> subdir-y += broadcom
> subdir-y += cavium
> subdir-y += exynos
> diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blaize/Makefile
> new file mode 100644
> index 000000000000..595e7a350300
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_BLAIZE_BLZP1600) += blaize-blzp1600-cb2.dtb
> diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
> new file mode 100644
> index 000000000000..0bdec7e81380
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: GPL-2.0
Preferred license is GPL-2.0 plus a permissive license.
> +/*
> + * Copyright (c) 2023 Blaize, Inc. All rights reserved.
2024 now.
> + */
> +
> +/dts-v1/;
> +
> +#include "blaize-blzp1600-som.dtsi"
> +#include <dt-bindings/net/ti-dp83867.h>
> +
> +/ {
> + model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
> +
> + compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200";
> + };
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + status = "okay";
> +
> + gpio_expander: gpio@74 {
> + compatible = "ti,tca9539";
> + reg = <0x74>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-line-names = "RSP_PIN_7", /* GPIO_0 */
> + "RSP_PIN_11", /* GPIO_1 */
> + "RSP_PIN_13", /* GPIO_2 */
> + "RSP_PIN_15", /* GPIO_3 */
> + "RSP_PIN_27", /* GPIO_4 */
> + "RSP_PIN_29", /* GPIO_5 */
> + "RSP_PIN_31", /* GPIO_6 */
> + "RSP_PIN_33", /* GPIO_7 */
> + "RSP_PIN_37", /* GPIO_8 */
> + "RSP_PIN_16", /* GPIO_9 */
> + "RSP_PIN_18", /* GPIO_10 */
> + "RSP_PIN_22", /* GPIO_11 */
> + "RSP_PIN_28", /* GPIO_12 */
> + "RSP_PIN_32", /* GPIO_13 */
> + "RSP_PIN_36", /* GPIO_14 */
> + "TP31"; /* GPIO_15 */
> + };
> +
> + gpio_expander_m2: gpio@75 {
> + compatible = "ti,tca9539";
> + reg = <0x75>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */
> + "M2_W_DIS2_N", /* GPIO_1 */
> + "M2_UART_WAKE_N", /* GPIO_2 */
> + "M2_COEX3", /* GPIO_3 */
> + "M2_COEX_RXD", /* GPIO_4 */
> + "M2_COEX_TXD", /* GPIO_5 */
> + "M2_VENDOR_PIN40", /* GPIO_6 */
> + "M2_VENDOR_PIN42", /* GPIO_7 */
> + "M2_VENDOR_PIN38", /* GPIO_8 */
> + "M2_SDIO_RST_N", /* GPIO_9 */
> + "M2_SDIO_WAKE_N", /* GPIO_10 */
> + "M2_PETN1", /* GPIO_11 */
> + "M2_PERP1", /* GPIO_12 */
> + "M2_PERN1", /* GPIO_13 */
> + "UIM_SWP", /* GPIO_14 */
> + "UART1_TO_RSP"; /* GPIO_15 */
> + };
> +};
> diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
> new file mode 100644
> index 000000000000..efac0d6b3d60
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2023 Blaize, Inc. All rights reserved.
> + */
> +
> +#include "blaize-blzp1600.dtsi"
> +
> +/ {
> + memory@1000 {
> + device_type = "memory";
> + reg = <0x0 0x00001000 0xfffff000>;
Memory starting at 4K. That's odd. I suspect you have something
reserved there and memory really starts at 0? If so, it is preferred
that you describe memory including that 4KB and then reserve it in
/memreserve/ section or /reserved-memory node.
> + };
> +};
> +
> +/* i2c4 bus is available only on the SoM, not on the board */
> +&i2c4 {
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
> new file mode 100644
> index 000000000000..26d8943d60ab
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
> @@ -0,0 +1,209 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2023 Blaize, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0 0x0>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0 0x1>;
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache0 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = /* Physical Secure PPI */
> + <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Physical Non-Secure PPI */
> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Hypervisor PPI */
> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Virtual PPI */
> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>;
> + };
> +
> + sram@0 {
> + /*
> + * On BLZP1600 there is no general purpose (non-secure) SRAM.
> + * A small DDR memory space has been reserved for general use.
> + */
> + compatible = "mmio-sram";
> + reg = <0x0 0x00000000 0x00001000>;
Ah, there it is. This isn't mmio-sram.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x00000000 0x1000>;
> +
> + /* SCMI reserved buffer space on DDR space */
> + scmi0_shm: scmi-sram@800 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x800 0x80>;
> + };
Just put this node into /reserved-memory.
> + };
> +
> + firmware {
> + scmi {
> + compatible = "arm,scmi-smc";
> + arm,smc-id = <0x82002000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + shmem = <&scmi0_shm>;
> +
> + scmi_clk: protocol@14 {
> + reg = <0x14>;
> + #clock-cells = <1>;
> + };
> +
> + scmi_rst: protocol@16 {
> + reg = <0x16>;
> + #reset-cells = <1>;
> + };
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges;
It is preferred if you limit this to actual ranges needed. Looks like
nothing below 0x200000000, but I imagine this is incomplete.
Rob
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^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v3 4/5] arm64: Add initial support for Blaize BLZP1600 CB2
@ 2024-04-25 16:56 ` Rob Herring
0 siblings, 0 replies; 28+ messages in thread
From: Rob Herring @ 2024-04-25 16:56 UTC (permalink / raw)
To: Niko Pasaloukos
Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, Neil Jones, Matt Redfearn, James Cowgill,
heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
On Thu, Apr 25, 2024 at 4:15 AM Niko Pasaloukos
<nikolaos.pasaloukos@blaize.com> wrote:
>
> Adds support for the Blaize CB2 development board based on
> BLZP1600 SoC. This consists of a Carrier-Board-2 and a SoM.
>
> The blaize-blzp1600.dtsi is the common part for the SoC,
> blaize-blzp1600-som.dtsi is the common part for the SoM and
> blaize-blzp1600-cb2.dts is the board specific file.
>
> Co-developed-by: James Cowgill <james.cowgill@blaize.com>
> Signed-off-by: James Cowgill <james.cowgill@blaize.com>
> Co-developed-by: Matt Redfearn <matt.redfearn@blaize.com>
> Signed-off-by: Matt Redfearn <matt.redfearn@blaize.com>
> Co-developed-by: Neil Jones <neil.jones@blaize.com>
> Signed-off-by: Neil Jones <neil.jones@blaize.com>
> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/blaize/Makefile | 2 +
> .../boot/dts/blaize/blaize-blzp1600-cb2.dts | 84 +++++++
> .../boot/dts/blaize/blaize-blzp1600-som.dtsi | 23 ++
> .../boot/dts/blaize/blaize-blzp1600.dtsi | 209 ++++++++++++++++++
> 5 files changed, 319 insertions(+)
> create mode 100644 arch/arm64/boot/dts/blaize/Makefile
> create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
> create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
> create mode 100644 arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 30dd6347a929..601b6381ea0c 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -9,6 +9,7 @@ subdir-y += apm
> subdir-y += apple
> subdir-y += arm
> subdir-y += bitmain
> +subdir-y += blaize
> subdir-y += broadcom
> subdir-y += cavium
> subdir-y += exynos
> diff --git a/arch/arm64/boot/dts/blaize/Makefile b/arch/arm64/boot/dts/blaize/Makefile
> new file mode 100644
> index 000000000000..595e7a350300
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_BLAIZE_BLZP1600) += blaize-blzp1600-cb2.dtb
> diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
> new file mode 100644
> index 000000000000..0bdec7e81380
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: GPL-2.0
Preferred license is GPL-2.0 plus a permissive license.
> +/*
> + * Copyright (c) 2023 Blaize, Inc. All rights reserved.
2024 now.
> + */
> +
> +/dts-v1/;
> +
> +#include "blaize-blzp1600-som.dtsi"
> +#include <dt-bindings/net/ti-dp83867.h>
> +
> +/ {
> + model = "Blaize BLZP1600 SoM1600P CB2 Development Board";
> +
> + compatible = "blaize,blzp1600-cb2", "blaize,blzp1600";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200";
> + };
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + status = "okay";
> +
> + gpio_expander: gpio@74 {
> + compatible = "ti,tca9539";
> + reg = <0x74>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-line-names = "RSP_PIN_7", /* GPIO_0 */
> + "RSP_PIN_11", /* GPIO_1 */
> + "RSP_PIN_13", /* GPIO_2 */
> + "RSP_PIN_15", /* GPIO_3 */
> + "RSP_PIN_27", /* GPIO_4 */
> + "RSP_PIN_29", /* GPIO_5 */
> + "RSP_PIN_31", /* GPIO_6 */
> + "RSP_PIN_33", /* GPIO_7 */
> + "RSP_PIN_37", /* GPIO_8 */
> + "RSP_PIN_16", /* GPIO_9 */
> + "RSP_PIN_18", /* GPIO_10 */
> + "RSP_PIN_22", /* GPIO_11 */
> + "RSP_PIN_28", /* GPIO_12 */
> + "RSP_PIN_32", /* GPIO_13 */
> + "RSP_PIN_36", /* GPIO_14 */
> + "TP31"; /* GPIO_15 */
> + };
> +
> + gpio_expander_m2: gpio@75 {
> + compatible = "ti,tca9539";
> + reg = <0x75>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */
> + "M2_W_DIS2_N", /* GPIO_1 */
> + "M2_UART_WAKE_N", /* GPIO_2 */
> + "M2_COEX3", /* GPIO_3 */
> + "M2_COEX_RXD", /* GPIO_4 */
> + "M2_COEX_TXD", /* GPIO_5 */
> + "M2_VENDOR_PIN40", /* GPIO_6 */
> + "M2_VENDOR_PIN42", /* GPIO_7 */
> + "M2_VENDOR_PIN38", /* GPIO_8 */
> + "M2_SDIO_RST_N", /* GPIO_9 */
> + "M2_SDIO_WAKE_N", /* GPIO_10 */
> + "M2_PETN1", /* GPIO_11 */
> + "M2_PERP1", /* GPIO_12 */
> + "M2_PERN1", /* GPIO_13 */
> + "UIM_SWP", /* GPIO_14 */
> + "UART1_TO_RSP"; /* GPIO_15 */
> + };
> +};
> diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
> new file mode 100644
> index 000000000000..efac0d6b3d60
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-som.dtsi
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2023 Blaize, Inc. All rights reserved.
> + */
> +
> +#include "blaize-blzp1600.dtsi"
> +
> +/ {
> + memory@1000 {
> + device_type = "memory";
> + reg = <0x0 0x00001000 0xfffff000>;
Memory starting at 4K. That's odd. I suspect you have something
reserved there and memory really starts at 0? If so, it is preferred
that you describe memory including that 4KB and then reserve it in
/memreserve/ section or /reserved-memory node.
> + };
> +};
> +
> +/* i2c4 bus is available only on the SoM, not on the board */
> +&i2c4 {
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
> new file mode 100644
> index 000000000000..26d8943d60ab
> --- /dev/null
> +++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
> @@ -0,0 +1,209 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2023 Blaize, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0 0x0>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0 0x1>;
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache0 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = /* Physical Secure PPI */
> + <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Physical Non-Secure PPI */
> + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Hypervisor PPI */
> + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + /* Virtual PPI */
> + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x3) |
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>;
> + };
> +
> + sram@0 {
> + /*
> + * On BLZP1600 there is no general purpose (non-secure) SRAM.
> + * A small DDR memory space has been reserved for general use.
> + */
> + compatible = "mmio-sram";
> + reg = <0x0 0x00000000 0x00001000>;
Ah, there it is. This isn't mmio-sram.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x00000000 0x1000>;
> +
> + /* SCMI reserved buffer space on DDR space */
> + scmi0_shm: scmi-sram@800 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x800 0x80>;
> + };
Just put this node into /reserved-memory.
> + };
> +
> + firmware {
> + scmi {
> + compatible = "arm,scmi-smc";
> + arm,smc-id = <0x82002000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + shmem = <&scmi0_shm>;
> +
> + scmi_clk: protocol@14 {
> + reg = <0x14>;
> + #clock-cells = <1>;
> + };
> +
> + scmi_rst: protocol@16 {
> + reg = <0x16>;
> + #reset-cells = <1>;
> + };
> + };
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges;
It is preferred if you limit this to actual ranges needed. Looks like
nothing below 0x200000000, but I imagine this is incomplete.
Rob
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v3 5/5] arm64: defconfig: Enable ARCH_BLAIZE_BLZP1600
2024-04-25 9:15 ` Niko Pasaloukos
@ 2024-04-25 9:15 ` Niko Pasaloukos
-1 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Enable ARCH_BLAIZE_BLZP1600 to get proper build coverage.
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2c30d617e180..7d368a8911bf 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -43,6 +43,7 @@ CONFIG_ARCH_BCM_IPROC=y
CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
+CONFIG_ARCH_BLAIZE_BLZP1600=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 5/5] arm64: defconfig: Enable ARCH_BLAIZE_BLZP1600
@ 2024-04-25 9:15 ` Niko Pasaloukos
0 siblings, 0 replies; 28+ messages in thread
From: Niko Pasaloukos @ 2024-04-25 9:15 UTC (permalink / raw)
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Niko Pasaloukos, Neil Jones,
Matt Redfearn, James Cowgill, heiko.stuebner@cherry.de,
shawnguo@kernel.org, macromorgan@hotmail.com, sre@kernel.org,
hvilleneuve@dimonoff.com, andre.przywara@arm.com,
rafal@milecki.pl, linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Enable ARCH_BLAIZE_BLZP1600 to get proper build coverage.
Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2c30d617e180..7d368a8911bf 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -43,6 +43,7 @@ CONFIG_ARCH_BCM_IPROC=y
CONFIG_ARCH_BCMBCA=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_BERLIN=y
+CONFIG_ARCH_BLAIZE_BLZP1600=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
--
2.34.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v3 0/5] Add support for Blaize BLZP1600 SoC
2024-04-25 9:15 ` Niko Pasaloukos
@ 2024-04-25 16:08 ` Conor Dooley
-1 siblings, 0 replies; 28+ messages in thread
From: Conor Dooley @ 2024-04-25 16:08 UTC (permalink / raw)
To: Niko Pasaloukos
Cc: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Neil Jones, Matt Redfearn,
James Cowgill, heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
[-- Attachment #1.1: Type: text/plain, Size: 1806 bytes --]
On Thu, Apr 25, 2024 at 09:15:02AM +0000, Niko Pasaloukos wrote:
> Adds basic support for the Blaize BLZP1600 SoC.
> This SoC contains two cores of Cortex-A53 CPUs, one Blaize
> Graph Streaming Processor (GSP) and several other IPs.
>
> V3 changes:
> * Removed unnecessary dt-bindings
> * Update SoBs
>
> V2 changes:
> * Update SoBs
> * `make dtbs_check` has no warnings
> * Fix dts names and removed dead code
> * DTS is separated from anything else
>
> Nikolaos Pasaloukos (5):
> dt-bindings: Add Blaize vendor prefix
> dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
> arm64: Add Blaize BLZP1600 SoC family
> arm64: Add initial support for Blaize BLZP1600 CB2
> arm64: defconfig: Enable ARCH_BLAIZE_BLZP1600
>
> .../devicetree/bindings/arm/blaize.yaml | 40 ++++
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> arch/arm64/Kconfig.platforms | 5 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/blaize/Makefile | 2 +
> .../boot/dts/blaize/blaize-blzp1600-cb2.dts | 84 +++++++
> .../boot/dts/blaize/blaize-blzp1600-som.dtsi | 23 ++
> .../boot/dts/blaize/blaize-blzp1600.dtsi | 209 ++++++++++++++++++
> arch/arm64/configs/defconfig | 1 +
I dunno if you've yet had any comment from Arnd on this series, but I'd
expect that the blaize patches follow the same path via the soc tree as
any other platform. I presume either you or one of the other Blaize guys
on this patchset will be taking care of that, so it would be a good idea
to add a MAINTAINERs entry covering the new arch/arm64/boot/dts/blaize
directory. There should be some more info about some of the expectations
at:
https://docs.kernel.org/process/maintainer-soc.html
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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 0/5] Add support for Blaize BLZP1600 SoC
@ 2024-04-25 16:08 ` Conor Dooley
0 siblings, 0 replies; 28+ messages in thread
From: Conor Dooley @ 2024-04-25 16:08 UTC (permalink / raw)
To: Niko Pasaloukos
Cc: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, Neil Jones, Matt Redfearn,
James Cowgill, heiko.stuebner@cherry.de, shawnguo@kernel.org,
macromorgan@hotmail.com, sre@kernel.org, hvilleneuve@dimonoff.com,
andre.przywara@arm.com, rafal@milecki.pl,
linus.walleij@linaro.org, andersson@kernel.org,
konrad.dybcio@linaro.org, geert+renesas@glider.be,
neil.armstrong@linaro.org, m.szyprowski@samsung.com,
nfraprado@collabora.com, u-kumar1@ti.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
[-- Attachment #1: Type: text/plain, Size: 1806 bytes --]
On Thu, Apr 25, 2024 at 09:15:02AM +0000, Niko Pasaloukos wrote:
> Adds basic support for the Blaize BLZP1600 SoC.
> This SoC contains two cores of Cortex-A53 CPUs, one Blaize
> Graph Streaming Processor (GSP) and several other IPs.
>
> V3 changes:
> * Removed unnecessary dt-bindings
> * Update SoBs
>
> V2 changes:
> * Update SoBs
> * `make dtbs_check` has no warnings
> * Fix dts names and removed dead code
> * DTS is separated from anything else
>
> Nikolaos Pasaloukos (5):
> dt-bindings: Add Blaize vendor prefix
> dt-bindings: arm: blaize: Add Blaize BLZP1600 SoC
> arm64: Add Blaize BLZP1600 SoC family
> arm64: Add initial support for Blaize BLZP1600 CB2
> arm64: defconfig: Enable ARCH_BLAIZE_BLZP1600
>
> .../devicetree/bindings/arm/blaize.yaml | 40 ++++
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> arch/arm64/Kconfig.platforms | 5 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/blaize/Makefile | 2 +
> .../boot/dts/blaize/blaize-blzp1600-cb2.dts | 84 +++++++
> .../boot/dts/blaize/blaize-blzp1600-som.dtsi | 23 ++
> .../boot/dts/blaize/blaize-blzp1600.dtsi | 209 ++++++++++++++++++
> arch/arm64/configs/defconfig | 1 +
I dunno if you've yet had any comment from Arnd on this series, but I'd
expect that the blaize patches follow the same path via the soc tree as
any other platform. I presume either you or one of the other Blaize guys
on this patchset will be taking care of that, so it would be a good idea
to add a MAINTAINERs entry covering the new arch/arm64/boot/dts/blaize
directory. There should be some more info about some of the expectations
at:
https://docs.kernel.org/process/maintainer-soc.html
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^ permalink raw reply [flat|nested] 28+ messages in thread