[linux-next:master 7867/8170] drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn401.c:501:9: sparse: sparse: static assertion failed: "DMUB command size mismatch"

[linux-next:master 7867/8170] drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn401.c:501:9: sparse: sparse: static assertion failed: "DMUB command size mismatch"

[kernel test robot]

:::::: 
:::::: Manual check reason: "low confidence static check first_new_problem: drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn401.c:501:9: sparse: sparse: static assertion failed: "DMUB command size mismatch""
:::::: 

BCC: lkp@intel.com
CC: oe-kbuild-all@lists.linux.dev
CC: Linux Memory Management List <linux-mm@kvack.org>
TO: Aurabindo Pillai <aurabindo.pillai@amd.com>
CC: Alex Deucher <alexander.deucher@amd.com>

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   5e4f84f18c4ee9b0ccdc19e39b7de41df21699dd
commit: 3dc4c954031129a68ba68c99b1803d775ee78258 [7867/8170] drm/amd/display: Add DCN401 dependant changes for DMCUB
:::::: branch date: 26 hours ago
:::::: commit date: 2 days ago
config: mips-randconfig-r131-20240425 (https://download.01.org/0day-ci/archive/20240425/202404251956.riTlbHss-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240425/202404251956.riTlbHss-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/r/202404251956.riTlbHss-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn401.c:501:9: sparse: sparse: static assertion failed: "DMUB command size mismatch"
   drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn401.c:537:9: sparse: sparse: static assertion failed: "DMUB command size mismatch"

vim +501 drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_dcn401.c

3df48ddedee4b6 Aurabindo Pillai 2024-04-19  495  
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  496  void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  497  		union dmub_rb_cmd *cmd)
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  498  {
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  499  	uint32_t *dwords = (uint32_t *)cmd;
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  500  
3df48ddedee4b6 Aurabindo Pillai 2024-04-19 @501  	static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch");
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  502  
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  503  	REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[0]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  504  	REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[1]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  505  	REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[2]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  506  	REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[3]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  507  	REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[4]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  508  	REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[5]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  509  	REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[6]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  510  	REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[7]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  511  	REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[8]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  512  	REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[9]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  513  	REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[10]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  514  	REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[11]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  515  	REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[12]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  516  	REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[13]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  517  	REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[14]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  518  	/* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  519  	 * interrupt.
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  520  	 */
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  521  	REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[15]);
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  522  }
3df48ddedee4b6 Aurabindo Pillai 2024-04-19  523  

:::::: The code at line 501 was first introduced by commit
:::::: 3df48ddedee4b68787087cdbdbec8fa28ad0ce68 drm/amd/display: Add new DCN401 sources

:::::: TO: Aurabindo Pillai <aurabindo.pillai@amd.com>
:::::: CC: Alex Deucher <alexander.deucher@amd.com>

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