[cip:linux-5.10.y-cip-rebase 894/928] drivers/clk/renesas/rzg2l-cpg.c:293:50: warning: passing argument 1 of 'clk_mux_index_to_val' discards 'const' qualifier from pointer target type

[cip:linux-5.10.y-cip-rebase 894/928] drivers/clk/renesas/rzg2l-cpg.c:293:50: warning: passing argument 1 of 'clk_mux_index_to_val' discards 'const' qualifier from pointer target type

[kernel test robot]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git linux-5.10.y-cip-rebase
head:   7bfc6836ad1b96dfdfd7ea91ffdee67d0d78254e
commit: ef51a13f0720a767a067eb7389fed926a9237fe1 [894/928] clk: renesas: rzg2l: Refactor SD mux driver
config: i386-allmodconfig (https://download.01.org/0day-ci/archive/20240511/202405112230.YvUZCVyV-lkp@intel.com/config)
compiler: gcc-13 (Ubuntu 13.2.0-4ubuntu3) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240511/202405112230.YvUZCVyV-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405112230.YvUZCVyV-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/clk/renesas/rzg2l-cpg.c: In function 'rzg2l_cpg_sd_clk_mux_set_parent':
>> drivers/clk/renesas/rzg2l-cpg.c:293:50: warning: passing argument 1 of 'clk_mux_index_to_val' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
     293 |         val = clk_mux_index_to_val(sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, index);
         |                                    ~~~~~~~~~~~~~~^~~~~~~~
   In file included from drivers/clk/renesas/rzg2l-cpg.c:16:
   include/linux/clk-provider.h:928:40: note: expected 'u32 *' {aka 'unsigned int *'} but argument is of type 'const u32 *' {aka 'const unsigned int *'}
     928 | unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
         |                                   ~~~~~^~~~~
   drivers/clk/renesas/rzg2l-cpg.c: In function 'rzg2l_cpg_sd_clk_mux_get_parent':
>> drivers/clk/renesas/rzg2l-cpg.c:321:55: warning: passing argument 2 of 'clk_mux_val_to_index' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]
     321 |         return clk_mux_val_to_index(hw, sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, val);
         |                                         ~~~~~~~~~~~~~~^~~~~~~~
   include/linux/clk-provider.h:926:50: note: expected 'u32 *' {aka 'unsigned int *'} but argument is of type 'const u32 *' {aka 'const unsigned int *'}
     926 | int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
         |                                             ~~~~~^~~~~


vim +293 drivers/clk/renesas/rzg2l-cpg.c

   281	
   282	static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
   283	{
   284		struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
   285		struct sd_mux_hw_data *sd_mux_hw_data = to_sd_mux_hw_data(clk_hw_data);
   286		struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
   287		u32 off = GET_REG_OFFSET(clk_hw_data->conf);
   288		u32 shift = GET_SHIFT(clk_hw_data->conf);
   289		unsigned long flags;
   290		u32 val;
   291		int ret;
   292	
 > 293		val = clk_mux_index_to_val(sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, index);
   294	
   295		spin_lock_irqsave(&priv->rmw_lock, flags);
   296	
   297		writel((CPG_WEN_BIT | val) << shift, priv->base + off);
   298	
   299		/* Wait for the update done. */
   300		ret = rzg2l_cpg_wait_clk_update_done(priv->base, clk_hw_data->sconf);
   301	
   302		spin_unlock_irqrestore(&priv->rmw_lock, flags);
   303	
   304		if (ret)
   305			dev_err(priv->dev, "Failed to switch parent\n");
   306	
   307		return ret;
   308	}
   309	
   310	static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
   311	{
   312		struct clk_hw_data *clk_hw_data = to_clk_hw_data(hw);
   313		struct sd_mux_hw_data *sd_mux_hw_data = to_sd_mux_hw_data(clk_hw_data);
   314		struct rzg2l_cpg_priv *priv = clk_hw_data->priv;
   315		u32 val;
   316	
   317		val = readl(priv->base + GET_REG_OFFSET(clk_hw_data->conf));
   318		val >>= GET_SHIFT(clk_hw_data->conf);
   319		val &= GENMASK(GET_WIDTH(clk_hw_data->conf) - 1, 0);
   320	
 > 321		return clk_mux_val_to_index(hw, sd_mux_hw_data->mtable, CLK_MUX_ROUND_CLOSEST, val);
   322	}
   323	

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