From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
qemu-devel@nongnu.org,
Daniel Henrique Barboza <danielhb413@gmail.com>,
Glenn Miles <milesg@linux.vnet.ibm.com>
Subject: [PATCH 12/14] target/ppc: Implement LDBAR, TTR SPRs
Date: Sat, 18 May 2024 19:31:54 +1000 [thread overview]
Message-ID: <20240518093157.407144-13-npiggin@gmail.com> (raw)
In-Reply-To: <20240518093157.407144-1-npiggin@gmail.com>
LDBAR, TTR are a Power-specific SPRs. These simple implementations
are enough for IBM proprietary firmware for now.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 10 ++++++++++
2 files changed, 12 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 9a51e54c1c..a014efc23a 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2098,6 +2098,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_DEXCR (0x33C)
#define SPR_IC (0x350)
#define SPR_VTB (0x351)
+#define SPR_LDBAR (0x352)
#define SPR_MMCRC (0x353)
#define SPR_PSSCR (0x357)
#define SPR_440_INV0 (0x370)
@@ -2144,6 +2145,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_440_IVLIM (0x399)
#define SPR_TSCR (0x399)
#define SPR_750_DMAU (0x39A)
+#define SPR_POWER_TTR (0x39A)
#define SPR_750_DMAL (0x39B)
#define SPR_440_RSTCFG (0x39B)
#define SPR_BOOKE_DCDBTRL (0x39C)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index dc6b4fc569..4591a68cc5 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5784,6 +5784,16 @@ static void register_power_common_book4_sprs(CPUPPCState *env)
&spr_access_nop, &spr_write_generic,
&spr_access_nop, &spr_write_generic,
0x00000000);
+ spr_register_hv(env, SPR_LDBAR, "LDBAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_core_lpar_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_POWER_TTR, "TTR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_core_write_generic,
+ 0x00000000);
#endif
}
--
2.43.0
next prev parent reply other threads:[~2024-05-18 9:34 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-18 9:31 [PATCH 00/14] target/ppc: Various TCG emulation patches Nicholas Piggin
2024-05-18 9:31 ` [PATCH 01/14] target/ppc: larx/stcx generation need only apply DEF_MEMOP() once Nicholas Piggin
2024-05-18 10:58 ` Richard Henderson
2024-05-18 9:31 ` [PATCH 02/14] target/ppc: Remove redundant MEMOP_GET_SIZE macro Nicholas Piggin
2024-05-18 9:57 ` BALATON Zoltan
2024-05-18 10:59 ` Richard Henderson
2024-05-18 9:31 ` [PATCH 03/14] target/ppc: Make checkstop actually stop the system Nicholas Piggin
2024-05-18 9:31 ` [PATCH 04/14] target/ppc: improve checkstop logging Nicholas Piggin
2024-05-18 9:31 ` [PATCH 05/14] target/ppc: Implement attn instruction on BookS 64-bit processors Nicholas Piggin
2024-05-18 11:05 ` Richard Henderson
2024-05-20 7:18 ` Nicholas Piggin
2024-05-18 11:07 ` Richard Henderson
2024-05-20 7:22 ` Nicholas Piggin
2024-05-18 9:31 ` [PATCH 06/14] target/ppc: BookE DECAR SPR is 32-bit Nicholas Piggin
2024-05-18 9:31 ` [PATCH 07/14] target/ppc: Wire up BookE ATB registers for e500 family Nicholas Piggin
2024-05-18 9:31 ` [PATCH 08/14] target/ppc: Add PPR32 SPR Nicholas Piggin
2024-05-18 9:31 ` [PATCH 09/14] target/ppc: add helper to write per-LPAR SPRs Nicholas Piggin
2024-05-18 11:26 ` Richard Henderson
2024-05-20 7:23 ` Nicholas Piggin
2024-05-18 9:31 ` [PATCH 10/14] target/ppc: Add SMT support to simple SPRs Nicholas Piggin
2024-05-18 9:31 ` [PATCH 11/14] target/ppc: Add SMT support to PTCR SPR Nicholas Piggin
2024-05-18 9:31 ` Nicholas Piggin [this message]
2024-05-18 9:31 ` [PATCH 13/14] target/ppc: Implement SPRC/SPRD SPRs Nicholas Piggin
2024-05-18 9:31 ` [PATCH 14/14] target/ppc: add SMT support to msgsnd broadcast Nicholas Piggin
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